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Combined DMOS and a vertical bipolar transistor device and fabrication method therefor

  • US 4,344,081 A
  • Filed: 04/14/1980
  • Issued: 08/10/1982
  • Est. Priority Date: 04/14/1980
  • Status: Expired due to Term
First Claim
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1. A combined MOS-bipolar semiconductor device comprising, in combination,a semiconductor body having at least one major surface including a surface portion of one conductivity type;

  • first and second spaced regions of opposite conductivity type formed in said body and abutting said major surface, third and fourth regions of said one conductivity type formed in said first and second regions, respectively, abutting said major surface and defining at least one channel region and at least one bipolar transistor;

    an insulating layer on said major surface;

    gate electrode means formed on said insulating layer over said channel region for forming an MOS transistor,separate electrical contact means to said first region, said third region, and said gate electrode means for permitting separate turn-on of said MOS transistor and said bipolar transistor.

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