Combined DMOS and a vertical bipolar transistor device and fabrication method therefor

• US 4,344,081 A
• Filed: 04/14/1980
• Issued: 08/10/1982
• Est. Priority Date: 04/14/1980
• Status: Expired due to Term

• Current Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Original Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Inventors: Blanchard, Richard A., Choy, Benedict C. K., Pao, Henry C.
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/139,793
• Time in Patent Office: 848 Days
• Field of Search: 357/43, 357/23, 357/35, 357/41
• US Class Current: 257/378
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

This disclosure relates to an improved DMOS semiconductor type device which can function both as a DMOS (unipolar) type device and as a bipolar transistor device. The DMOS device has two separated source regions of, for example, N+ conductivity and each of these source regions is surrounded by a P- type region, thus providing a pair of channels between each N+ source region and a common N type drain region located between the P- regions. A gate electrode is disposed over both of the channels and functions to permit electrons from the N+ source regions to flow across the P- channels into the common N type drain region when a proper bias is applied to the gate region. Each of the source regions has its own electrode and a separate electrode is provided to each of the P- regions that surround each of the respective N+ source regions. Thus, the DMOS type structure can function as a DMOS device with the electrodes to the source regions serving as source electrodes and the gate electrode functioning to permit electron flow from the separated source regions to a common drain region. Alternatively, one of the electrodes to the N+ source region could function as an emitter (or a source electrode for MOS operation) electrode with the electrode to the surrounding P- region serving as a base electrode. To complete the bipolar vertical transistor, a collector electrode is provided electrically coupled to the N- region. Alternatively, the collector electrode serves as the drain electrode if the device is operated as a DMOS device.

Claims

1. A combined MOS-bipolar semiconductor device comprising, in combination,

a semiconductor body having at least one major surface including a surface portion of one conductivity type;

first and second spaced regions of opposite conductivity type formed in said body and abutting said major surface, third and fourth regions of said one conductivity type formed in said first and second regions, respectively, abutting said major surface and defining at least one channel region and at least one bipolar transistor;

an insulating layer on said major surface;

gate electrode means formed on said insulating layer over said channel region for forming an MOS transistor,

separate electrical contact means to said first region, said third region, and said gate electrode means for permitting separate turn-on of said MOS transistor and said bipolar transistor.

2. The device of claim 1 wherein said MOS transistor comprises a DMOS transistor.

3. The device of claim 1 wherein said first region is the base and said third region is the emitter of said bipolar transistor.

4. The device of claim 1 wherein said electrical contact means to said first region permitting both turn-on and turn-off of said bipolar transistor.