High speed data transfer for a semiconductor memory

• US 4,344,156 A
• Filed: 10/10/1980
• Issued: 08/10/1982
• Est. Priority Date: 10/10/1980
• Status: Expired due to Term

• Current Assignee: Inmos Corp (STMicroelectronics NV)
• Original Assignee: Inmos Corp (STMicroelectronics NV)
• Inventors: Wooten, David R., Eaton, Sargent S. Jr.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/195,729
• Time in Patent Office: 669 Days
• Field of Search: 365/189, 365/230, 365/203
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

Claims

1. In a semiconductor memory, a system for rapidly transferring data between a plurality of successive memory locations and a data output buss in response to a single address input, comprising:

a plurality of N data latches for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input;

a corresponding plurality of N serially connected decoders each associated with one of said data latches, each adapted to be enabled for causing its associated data latch to output its stored data to the data buss, and each receiving selected bits of the address input such that one of the decoders is initially enabled, in response to said selected bits having a given logic state, for causing its associated data latch to output its stored data to the data buss,

the enabled decoder being adapted to then disable itself and to enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N successive bits of data in response to a single address input.

2. A system as set forth in claim 1 including a plurality of input buffers for writing input data into memory locations, wherein each of said decoders is associated with an input buffer, and wherein said decoders are responsive to a single address input for selecting said buffers sequentially so as to write the input data into successive memory locations.

3. A system as set forth in claim 2 wherein each buffer includes an input for receiving data, an output for coupling data to memory, and means for holding the data at its output while successive buffers are selected such that writing of the data at a buffer output may continue while successive buffers are selected.

4. A system as set forth in claim 3 wherein each buffer includes a hold-off circuit for rendering the buffer insensitive to data received at its input while its associated decoder is disabled.

5. A system as set forth in claim 1 wherein each decoder includes:

an address-input circuit receiving the selected address bits for developing an output signal in response to the selected address bits being in a given logic state;

means for coupling said output signal to an associated data latch for causing said data latch to output its stored data; and

a disabling circuit coupled to said address-input circuit, receiving the latter circuit'"'"'s output signal and a clock signal, and being responsive to said control signal and to the clock signal for inhibiting the address-input circuit from developing a further output signal, whereby each decoder disables itself after having been enabled.

6. A system as set forth in claim 5 wherein each decoder further includes:

an enabling circuit coupled to said address-input circuit, receiving the output signal of a previous decoder and said clock signal, and responsive to the previous decoder'"'"'s output signal and the occurrence of said clock signal for enabling its address-input circuit to develop an output signal, whereby each decoder is enabled by a previously enabled decoder.

7. A system as set forth in claim 5 wherein said address-input circuit includes:

a first node adapted to be precharged to a positive voltage level;

transistor means receiving the address input bits for inhibiting the discharge of said first node in response to said address bits being in said given logic state;

a first transistor having a source coupled to said first node, having a gate receiving a second clock signal, and having a drain coupled to a second node;

a second transistor having a gate coupled to the second node, having a drain receiving a third clock signal, and a source output terminal for developing the control signal thereat,

said second clock signal being selected to go high to turn on the first transistor and precharge said second node, and then to go low so as to substantially cut off said first transistor and thereby isolate said first node from said second node,

said second clock signal being selected to go high while said first transistor is substantially cut off, to bootstrap said second node to a higher voltage via gate-to-drain capacitance associated with said second transistor and to drive the output terminal to a relatively high positive voltage.

8. In a semiconductor memory having a read mode and a write mode, a system for rapidly writing incoming data into four successive memory locations and for reading data out of four successive memory locations, comprising:

four data latches for storing data associated with four successive memory locations which are defined by a plurality of bits of the address input, each data latch being adapted to output its stored data when selected by an enabled decoder;

four data input buffers each having an input for receiving incoming data, an output for coupling the data to memory, and each being adapted to output the data to memory when selected by an enabled decoder;

four serially connected decoders, each associated with one of said data latches and with one of said input buffers, and each receiving selected bits of the address input such that one of the decoders is initially enabled in response to the address input for selecting its associated data latch when the memory is in a read mode and for selecting its associated input buffer when the memory is in a write mode,

the enabled decoder being adapted to disable itself and enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to rapidly write four bits of data into successive memory locations when the memory is in the write mode and to rapidly read four bits of data out of successive memory locations when the memory is in the read mode.

9. A system as set forth in claim 8 wherein each input buffer includes means for holding data at its output while successive input buffers are selected so that its data can continue to be read into memory after its associated decoder has been disabled.