Non-linear dynamic filtering device for the angular measuring of noise in a radar

• US 4,345,252 A
• Filed: 02/07/1980
• Issued: 08/17/1982
• Est. Priority Date: 02/13/1979
• Status: Expired due to Term

• Current Assignee: Thomson-CSF (Thales SA)
• Original Assignee: Thomson-CSF (Thales SA)
• Inventors: Carre, Roland, Doriath, Georges
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US06/119,397
• Time in Patent Office: 922 Days
• Field of Search: 343/16 M, 343/5 NQ
• US Class Current: 342/91
• CPC Class Codes: G01S 13/02 Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
• CPC Class Codes: G01S 13/4427 with means for eliminating the target-dependent errors in angle measurements, e.g. glint, scintillation effects
• CPC Class Codes: G01S 7/34 Gain of receiver varied automatically during pulse-recurrence period, e.g. anti-clutter gain control

Abstract

To improve the accuracy of angular measurements in a radar or sonar system by suppressing noise due to target glint, an angular-deviation signal ε derived from the output signals Σ and Δ of a sum channel and a difference channel is multiplied with a gain-control signal K(t) before being subjected to recursive filtering. Signal K(t) is obtained, also by recursive filtering, from a weighting function P(t) which goes to zero during periods when the measurement of the angular deviation is unreliable as determined from a low value of sum signal Σ and from a peaking of a quadrature deviation signal εq, function P(t) being proportional to the product Σⁿ ·(S-|εq|) where the exponent n is at least equal to 1 and S is a predetermined threshold. The recursive filter processing the deviation signal ε has two cross-connected stages, both controlled by signal K(t), respectively emitting a corrected deviation measurement ε and an estimated time differential τdε/dt, τ being a delay introduced in a recursive loop of each stage. Prior to being multiplied with gain-control signal K(t), the deviation signal ε may be additively combined with an angular-orientation signal θ_r of a radar antenna to yield an angular value θ_c which can then be multiplied by a measured target distance D to provide a transverse-deviation signal d; in that case the two filter stages respectively emit a corrected deviation signal d and a target-velocity estimate v.

Claims

1. A circuit arrangement for improving the accuracy of angular measurements in an echo-type target-locating system with a first reception channel emitting a sum signal Σ

, a second reception channel emitting a difference signal Δ

, and circuitry connected to said reception channels for deriving therefrom an angular-deviation signal ε and

a quadrature deviation signal ε

q respectively appearing on a first and a second output thereof, comprising;

first calculating means connected to said first reception channel and to said second output for generating a weighting function P(t) under the control of said sum signal Σ and

said quadrature deviation signal ε

q, said weighting function P(t) going to zero during periods in which the sum signal Σ

is low and the quadrature deviation signal ε

q is peaking;

second calculating means in cascade with said first calculating means for establishing a gain-control signal K(t) varying with said weighting function P(t); and

dynamic filter means connected to said second calculating means and to said first output for processing said angular-deviation signal ε

by multiplying same with said gain-control signal K(t) and subjecting the product to recursive filtering.

2. A circuit arrangement as defined in claim 1 wherein said dynamic filter means comprises two cross-connected stages with respective recursive loops each introducing a delay τ

, one of said stages emitting a corrected deviation signal, the other of said stages emitting an estimated time derivative of said corrected deviation signal multiplied by said delay τ

.

3. A circuit arrangement as defined in claim 2 wherein the loops of said stages each include a respective multiplier with an input connected to said second calculating means for receiving said gain-control signal K(t) therefrom.

4. A circuit arrangement as defined in claim 3 wherein the multiplier of said other of said stages has another input connected to an output of the multiplier of said one of said stages whereby the signal processed in said other of said stages is multiplied with the square of said gain-control signal K(t).

5. A circuit arrangement as defined in claim 2, further comprising an adder inserted between said first output and said dynamic filter means, said adder having one input receiving said angular-deviation signal ε

and another input connected to a position controller for a radar antenna for receiving therefrom an angular-orientation signal θ

_r to be additively combined with the angular-deviation signal ε

into an angular value θ

_c delivered to said dynamic filter means for processing.

6. A circuit arrangement as defined in claim 5, further comprising multiplying means inserted between said adder and said dynamic filter means, said multiplying means having an input connected to a further output of said circuitry for receiving therefrom a target-distance measurement D and delivering the product D·

θ

_c to said dynamic filter means whereby said other of said stages emits a target-velocity estimate v.

7. A circuit arrangement as defined in claim 1, 2, 3 or 4 wherein said first calculating means comprises a rectifier connected to said second output for generating an absolute value |ε

q| of said quadrature deviation signal ε

q, a subtractor connected to said rectifier and to a source of a predetermined threshold S for producing the difference S-|ε

q|, arithmetic means connected to said first reception channel and to said subtractor for producing said weighting function P(t) proportional to the product Σ

ⁿ ·

(S-|ε

q|) where n is an exponent equal to at least 1, said arithmetic means having an output connection to said second calculating means, said switch means in said output connection controlled by a comparator in parallel with said subtractor for blocking the transmission of said product to said second calculating means whenever said absolute value |ε

q| exceeds said threshold S.

8. A circuit arrangement as defined in claim 7 wherein said first calculating means further comprises a memory connected to said first reception channel via a gate controlled by said comparator for storing said sum signal Σ

as long as said absolute value |ε

q| exceeds said threshold S, and comparison means with inputs connected to said memory and to said first reception channel and with an output connected to said switch means for blocking said output connection independently of said comparator whenever the current value of said sum signal Σ

is less than the value last stored in said memory.

9. A circuit arrangement as defined in claim 1, 2, 3 or 4 wherein said second calculating means comprises a recursive loop including an adding circuit, a delay circuit and an amplifier in cascade, said adding circuit having an input connected to said first calculating means and another input connected to an output of said amplifier, and a divider having a dividend input connected in parallel with said adding circuit to said first calculating means and a divisor input connected in parallel with said delay circuit to the output of said adding circuit, said divider having an output emitting said gain-control signal K(t) as the quotients of signals appearing at said dividend and divisor inputs thereof.

10. A circuit arrangement as defined in claim 9 wherein said amplifier has a gain of less than unity.