MOS Power transistor with improved high-voltage capability

• US 4,345,265 A
• Filed: 04/14/1980
• Issued: 08/17/1982
• Est. Priority Date: 04/14/1980
• Status: Expired due to Term

• Current Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Original Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/139,654
• Time in Patent Office: 855 Days
• Field of Search: 357/23, 357/52, 357/41, 357/23 VT, 357/23 VD, 357/23 C, 357/23 S, 357/23 D, 357/23 CS, 357/23 R
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Device means for reducing latch-back breakdown thus raising the reverse-biased power capability of a DMOS transistor or the like. A DMOS transistor is an MOS field effect transistor comprising a lightly-doped (usually diffused) body region formed in a drain region; a heavily-doped source region is located in the body region in proximity to the drain. Since such a device structure also exhibits substantial bipolar transistor action, it is prone to latch-back breakdown. Means for reducing latch-back breakdown include providing a distributed diode with a lower breakdown voltage than the DMOS transistor to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region to reduce both the voltage and the voltage gradient in the base of the parasitic bipolar device. These means may be used singly or in combination.

Claims

1. An MOS transistor having improved breakdown characteristics comprising:

a drain region of first conductivity type;

a body region of a second conductivity type in said drain region and forming a P-N junction therewith;

a source region of said first conductivity type in said body region;

a gate for inducing a surface channel region in said body between said source and drain regions; and

low impedance means for reducing the breakdown voltage of said P-N junction away from said channel region, said means including a second region of said second conductivity type merged with said body region and extending further into said drain region than does said body region.

2. An MOS transistor in accordance with claim 1 wherein said means including a region of said second conductivity type is more heavily doped than said body region.

3. An MOS transistor in accordance with claim 1 wherein said second region of said second conductivity type merged with said body region and extending further into said drain region than does said body region and also extends beneath said source region.

4. An MOS transistor having improved breakdown characteristics comprising:

a substrate having a major surface;

a drain region of first conductivity type;

a body region of a second conductivity type in said drain region and forming a P-N junction therewith;

a source region of said first conductivity type in said body region, each of said drain, body, and source regions including said surface;

a gate for inducing a channel region at said surface in said body between said source and drain regions;

metallic shorting means making contact with said source region and electrically connecting it with said body region away from said channel region at said surface; and

shunt conductance means for reducing the resistance in said body region between said channel region and said shorting means, said means including a second region of said second conductivity type extending further into said drain region away from said surface than does said body region.

5. An MOS transistor in accordance with claim 4 having a plurality of source regions in a single body region, and said shunt conductance means comprising heavily-doped regions of second conductivity type interposed between said plurality of source regions at said surface and forming a portion of said body region.

6. An MOS transistor in accordance with claim 4 further including means for reducing the drain-body P-N junction breakdown voltage away from said channel region.

7. An MOS transistor in accordance with claim 4 wherein said second region of said second conductivity type also extends beneath said source region.

8. The transistor of claim 7 wherein said source region extends over only a portion of said second region of said second region of said second conductivity type.

9. An MOS transistor in accordance with claim 4 wherein said shunt conductance means comprises a plurality of heavily-doped regions of said second conductivity type merged with said body region, each of said heavily-doped regions being surrounded by said source region at said surface.

10. The MOS transistor of claim 9 wherein said plurality of heavily-doped regions of second conductivity type extend further into said drain region away from said surface than does said body region.

11. The MOS transistor of claim 10 wherein said drain region is flanked by a body region on at least two sides at said surface.

12. The MOS transistor of claim 11 wherein said drain region is surrounded by said body region at said surface.

13. The MOS transistor of claim 12 further comprising a body region flanked on two sides by said drain region at said surface.

14. An MOS device having improved breakdown characteristics comprising:

a primary body region of a first conductivity type;

a first region of a second conductivity type partially surrounding said body region and forming a P-N junction therewith;

a second region of said second conductivity type in said body region, said first and second regions being the drain and source regions respectively, of said MOS device;

gate means for controlling a surface channel region in said body between said first and second regions; and

low impedance means for reducing the breakdown of said P-N junction away from channel region, said means including an adjunct body region of said first conductivity type extending further into said drain region than does said body region.

15. A method for forming an MOS device comprising the steps of:

providing a primary body region of a first conductivity type;

providing a first region of a second conductivity type partially surrounding said body region and forming a P-N junction therewith;

providing a second region of said second conductivity type in said body region, said first and second regions being the drain and source regions respectively, of said MOS device;

providing a gate for controlling a surface channel region in said body between said first and second regions; and

providing low impedance means for reducing the breakdown of said P-N junction away from said channel region, said means including an adjunct body region of said first conductivity type extending further into said drain region than does said primary body region.