MOS Power transistor with improved high-voltage capability
First Claim
1. An MOS transistor having improved breakdown characteristics comprising:
- a drain region of first conductivity type;
a body region of a second conductivity type in said drain region and forming a P-N junction therewith;
a source region of said first conductivity type in said body region;
a gate for inducing a surface channel region in said body between said source and drain regions; and
low impedance means for reducing the breakdown voltage of said P-N junction away from said channel region, said means including a second region of said second conductivity type merged with said body region and extending further into said drain region than does said body region.
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Abstract
Device means for reducing latch-back breakdown thus raising the reverse-biased power capability of a DMOS transistor or the like. A DMOS transistor is an MOS field effect transistor comprising a lightly-doped (usually diffused) body region formed in a drain region; a heavily-doped source region is located in the body region in proximity to the drain. Since such a device structure also exhibits substantial bipolar transistor action, it is prone to latch-back breakdown. Means for reducing latch-back breakdown include providing a distributed diode with a lower breakdown voltage than the DMOS transistor to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region to reduce both the voltage and the voltage gradient in the base of the parasitic bipolar device. These means may be used singly or in combination.
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Citations
15 Claims
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1. An MOS transistor having improved breakdown characteristics comprising:
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a drain region of first conductivity type; a body region of a second conductivity type in said drain region and forming a P-N junction therewith; a source region of said first conductivity type in said body region; a gate for inducing a surface channel region in said body between said source and drain regions; and low impedance means for reducing the breakdown voltage of said P-N junction away from said channel region, said means including a second region of said second conductivity type merged with said body region and extending further into said drain region than does said body region. - View Dependent Claims (2, 3)
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4. An MOS transistor having improved breakdown characteristics comprising:
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a substrate having a major surface; a drain region of first conductivity type; a body region of a second conductivity type in said drain region and forming a P-N junction therewith; a source region of said first conductivity type in said body region, each of said drain, body, and source regions including said surface; a gate for inducing a channel region at said surface in said body between said source and drain regions; metallic shorting means making contact with said source region and electrically connecting it with said body region away from said channel region at said surface; and shunt conductance means for reducing the resistance in said body region between said channel region and said shorting means, said means including a second region of said second conductivity type extending further into said drain region away from said surface than does said body region. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An MOS device having improved breakdown characteristics comprising:
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a primary body region of a first conductivity type; a first region of a second conductivity type partially surrounding said body region and forming a P-N junction therewith; a second region of said second conductivity type in said body region, said first and second regions being the drain and source regions respectively, of said MOS device; gate means for controlling a surface channel region in said body between said first and second regions; and low impedance means for reducing the breakdown of said P-N junction away from channel region, said means including an adjunct body region of said first conductivity type extending further into said drain region than does said body region.
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15. A method for forming an MOS device comprising the steps of:
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providing a primary body region of a first conductivity type; providing a first region of a second conductivity type partially surrounding said body region and forming a P-N junction therewith; providing a second region of said second conductivity type in said body region, said first and second regions being the drain and source regions respectively, of said MOS device; providing a gate for controlling a surface channel region in said body between said first and second regions; and
providing low impedance means for reducing the breakdown of said P-N junction away from said channel region, said means including an adjunct body region of said first conductivity type extending further into said drain region than does said primary body region.
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Specification