Distance-measuring system with in-range signalling for use with cameras, alarms, and the like

• US 4,345,827 A
• Filed: 09/19/1980
• Issued: 08/24/1982
• Est. Priority Date: 09/27/1979
• Status: Expired due to Term

• Current Assignee: Agfa-Gevaert AG (Agfa-Gevaert N.V.)
• Original Assignee: Agfa-Gevaert AG (Agfa-Gevaert N.V.)
• Inventors: Lermann, Peter, Stemme, Otto, Cocron, Istvan
• Primary Examiner(s): Adams, Russell E.
• Application Number:
  US06/188,600
• Time in Patent Office: 704 Days
• Field of Search: 354/25 R, 354/25 A, 354/60 L
• US Class Current: 396/106
• CPC Class Codes: G01S 13/08 Systems for measuring distance only indirect measurement G01S13/46
• CPC Class Codes: G01S 17/08 for measuring distance only indirect measurement G01S17/46; active triangulation systems G01S17/48

Abstract

A distance measuring system generates an in-range signal when an object is located within a range of focus or a zone of protection, as the case may be. The system utilizes a single infrared transmitter and two receivers in order to determine the position of the object by triangulation.

Claims

1. In a control system for use in cameras and the like which utilizes a clocked radiation transmitter for periodically emitting pulses of radiation with a fixed frequency, amplitude and pulse duration, like first and second radiation receivers receiving the pulses and generating first and second received signals corresponding thereto, and a signal processing network including two channels for processing the first and second received signals so as to reduce background radiation and noise, an improvement for converting the first and second received signals to digital signals and indicating when an object is located within a range of focus comprising:

integrating means connected to the signal processing network and responding to the first and second received signals so as to produce first and second analog signals which are a time integrated transformation of the received signals;

threshold means connected to said integrating means and having threshold values which are large as compared to pulse amplitude and a noise component, the threshold means operating in a manner that digital input signals are produced which are characteristic of said analog signals and being logically high when the analog signals exceed the threshold values and being logically low otherwise;

storage means cooperating with said threshold means by storing said digital input signals and releasing the same in response to a pulse at the end of each measuring cycle of said transmitter;

control means including logical AND or OR gating members having inputs connected to said storage means so as to produce an in-range signal only upon the occurrence of a logically high digital input signal, two RC timing circuits, an additional AND gate having an input selectively connectable to the output of said AND gating member either directly or via one of said RC timing circuits, and another input connected via the other RC timing circuit to the output of said OR gating member; and

a first output terminal connected to the output of said OR gating member, a second output terminal connected to the output of said AND gating member, and a third output terminal connected to the output of said additional AND gate.

2. The improvement defined by claim 1, wherein the output stage includes a congruance monitor responsive to a condition in which both the first digital input signal and the second digital input signal are logically high simultaneously and generating a congruance signal in response thereto.

3. The improvement defined by claim 2, further including a first time delay delaying an in-range signal for a first predetermined delay period, and further including a second time delay delaying a congruance signal for a second predetermined delay period.

4. The improvement defined by claim 3, wherein the first time delay is connected to one input of a two input output gate and wherein the second time delay is connected to another input thereof, whereby when an in-range signal and a congruance signal are both generated, an output signal will be generated after said predetermined delay period.

5. The improvement defined by claim 1, further including a secondary clock a first clocked flip-flop into which the first digital input signal may be clocked by the secondary clock and a second clocked flip-flop into which the second digital input signal may be clocked by the secondary clock.

6. The improvement defined by claim 1 further comprising a first and second comparator stage;

each of the first and second comparator stages includes a reset pulse generator operating in a manner that after a corresponding high digital input signal is generated by a comparator stage, a reset pulse is generated and routed to the threshold means for starting a subsequent time-integration.

7. The improvement defined by claim 5, wherein the secondary clock is a self-resetting ring counter driven by clock pulses which are used to clock the transmitter.

8. The improvement defined by claim 7, wherein the ring counter operates in a manner that the first and second means are always operated to start a subsequent time-integration prior to a resetting of the ring counter.

9. The improvement defined by claim 8, wherein the ring counter includes:

a counter chip having a clocked input, an output and a reset input;

an OR-gate having a first input connected to the output of the counter chip, a second input connected to both of the reset pulse generators, and an output;

a first time delay stage having an input connected to the output of the OR-gate and an output connected to the first means and the second means; and

a second time-delay stage having an input connected to the output of the first time-delay stage and an output connected to the reset input of the counter chip.

10. The improvement defined by claim 6, wherein the comparator stages each include a first operational amplifier and a second operational amplifier in parallel therewith, said operational amplifiers being so biased that for a given digital input signal, the first operational amplifier will produce an output prior to a production of an output by the second operational amplifier.

11. The improvement defined by claim 5, wherein the secondary clock is a self-resetting ring counter driven by clock pulses which are used to clock the transmitter.

12. The improvement defined by claim 11, wherein the ring counter operates in a manner that the first and second means are always operated to start a subsequent time-integration prior to a resetting of the ring counter.

13. The improvement defined by claim 12, wherein the ring counter includes:

a counter chip having a clocked input, an output and a reset input;

an OR-gate having a first input connected to the output of the counter chip, a second input connected to both of the reset pulse generators, and an output;

a first time delay stage having an input connected to the output of the OR-gate and an output connected to the first means and the second means; and

a second time-delay stage having an input connected to the output of the first time-delay stage and an output connected to the reset input of the counter chip.

14. The improvement defined by claim 6, wherein the secondary clock is a self-resetting ring counter driven by clock pulses which are used to clock the transmitter.

15. The improvement defined by claim 14, wherein the ring counter operates in a manner that the first and second means are always operated to start a subsequent time-integration prior to a resetting of the ring counter.

16. The improvement defined by claim 15, wherein the ring counter includes:

a counter chip having a clocked input, an output and a reset input;

an OR-gate having a first input connected to the output of the counter chip, a second input connected to both of the reset pulse generators, and an output;

a first time delay stage having an input connected to the output of the OR-gate and an output connected to the first means and the second means; and

a second time-delay stage having an input connected to the output of the first time-delay stage and an output connected to the reset input of the counter chip.