Self-checking system for electronic processing equipment
First Claim
1. In a system for the control of a plurality of peripheral units by a processor programmed to exchanged information with said peripheral units,the combination therewith of a checking unit addressable by said processor during execution of a diagnostic program, said checking unit comprising:
- memory means storing a plurality of microprograms each involving the emission of code words in a succession of phases;
timing means responsive to reception of a memory address from said processor for reading out from said memory means to said processor, at a predetermined rate varying for different microprograms, code words pertaining to the successive phases of a microprogram identified by said memory address; and
alarm means triggerable by said processor to indicate a malfunction upon detection of a disparity between code words read out from said memory means and corresponding words simultaneously generated in said processor as part of the latter'"'"'s diagnostic program;
said timing means including a source of stepping pulses of variable cadence, selector means connected to said source for adjusting said cadence under the control of a memory address received from said processor, and a pulse counter connected to said source for advancement by said stepping pulses.
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Abstract
A central processor controlling a set of peripheral units through an associated logic network is programmed to activate from time to time, through a direct connection by-passing the logic network, a checking unit including a read-only memory storing a variety of microprograms in areas individually addressable by the processor. Upon the reception of a memory address, a timing circuit is set to determine the frequency of stepping pulses advancing a counter which calls forth successive phases of the selected mircroprogram. Code words read out during these phases to the logic network are fed back by the latter to the processor for comparison with corresponding contents of its own program memory; in the event of a disparity, or when failure of the processor to emit a resetting signal lets the counter advance to the limit of its capacity, an alarm indicator is tripped.
23 Citations
8 Claims
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1. In a system for the control of a plurality of peripheral units by a processor programmed to exchanged information with said peripheral units,
the combination therewith of a checking unit addressable by said processor during execution of a diagnostic program, said checking unit comprising: -
memory means storing a plurality of microprograms each involving the emission of code words in a succession of phases; timing means responsive to reception of a memory address from said processor for reading out from said memory means to said processor, at a predetermined rate varying for different microprograms, code words pertaining to the successive phases of a microprogram identified by said memory address; and alarm means triggerable by said processor to indicate a malfunction upon detection of a disparity between code words read out from said memory means and corresponding words simultaneously generated in said processor as part of the latter'"'"'s diagnostic program; said timing means including a source of stepping pulses of variable cadence, selector means connected to said source for adjusting said cadence under the control of a memory address received from said processor, and a pulse counter connected to said source for advancement by said stepping pulses. - View Dependent Claims (2, 3, 4, 5, 7, 8)
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6. In a system for the control of a plurality of peripheral units by a processor programmed to exchange information with said peripheral units through a central logic network,
the combination therewith of a checking unit addressable by said processor during execution of a diagnostic program, said checking unit comprising: -
memory means storing a plurality of microprograms each involving the emission of code words in a succession of phases; timing means responsive to reception of a memory address from said processor via a signal path independent of said logic network for reading out from said memory means to said processor through said logic network, at a predetermined rate, code words pertaining to the successive phases of a microprogram identified by said memory address; and alarm means triggerable by said processor to indicate a malfunction upon detection of a disparity between code words read out from said memory means and corresponding words simultaneously generated in said processor as part of the latter'"'"'s diagnostic program.
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Specification