Latchup resistant pseudorandom binary sequence generator
First Claim
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1. A pseudorandom binary sequence generator including means adapted thereto for providing latchup resistance, including in combination:
- a. a source of clock signal;
b. a shift register means coupled with said clock signal, having a data input thereto and plural stage outputs therefrom;
c. dynamic imbalance means coupled to at least one said stage output and cooperative therewith to produce at least one delayed output therefrom exceeding intrinsic transmission gate delay but less than said clock signal period;
d. combinational logic means directly coupled with two inputs between said stage output and said dynamic imbalance means output and an output coupled to said register data input, operative therebetween so as to produce a pseudorandom flow of binary pulses; and
further,e. whereby resistance to latchup is provided through the effective dynamic imbalance introduced by the time delay of the signal flow coupled between at least one said stage output and the said logic means.
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Abstract
A pseudorandom binary sequence generator employing a conditional feedback path between several individual outputs and the input of a clocked shift register. Enhanced reistance to a latchup condition is brought about by way of a delay of one of the outputs, relative to the other outputs, as coupled to the feedback path.
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Citations
9 Claims
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1. A pseudorandom binary sequence generator including means adapted thereto for providing latchup resistance, including in combination:
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a. a source of clock signal; b. a shift register means coupled with said clock signal, having a data input thereto and plural stage outputs therefrom; c. dynamic imbalance means coupled to at least one said stage output and cooperative therewith to produce at least one delayed output therefrom exceeding intrinsic transmission gate delay but less than said clock signal period; d. combinational logic means directly coupled with two inputs between said stage output and said dynamic imbalance means output and an output coupled to said register data input, operative therebetween so as to produce a pseudorandom flow of binary pulses; and
further,e. whereby resistance to latchup is provided through the effective dynamic imbalance introduced by the time delay of the signal flow coupled between at least one said stage output and the said logic means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification