Precise digitally programmed frequency source

• US 4,349,887 A
• Filed: 08/22/1980
• Issued: 09/14/1982
• Est. Priority Date: 08/22/1980
• Status: Expired due to Term

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: Crowley, Albert T.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/181,086
• Time in Patent Office: 753 Days
• Field of Search: 364/703, 364/721, 328/14
• US Class Current: 708/103
• CPC Class Codes: H03K 4/026 using digital techniques

Abstract

A digitally controlled oscillator for generating a plurality of signals spaced apart by very small frequency increments. The system comprises first means for generating a source signal of frequency f_c, second means responsive to said first signal to produce a first binary output signal of frequency Nf_c /2ⁿ, where n is a variable integer. Also provided are first frequency divider means responsive to said first binary output signal to produce a second binary output signal of frequency Nf_c /2^n+m, where m is another integer and second frequency divider means also responsive to said first signal f_c to produce a third binary output signal of frequency f_c /2^T. Further provided are logic means responsive to said second and third binary output signals to produce a fourth binary output signal of average frequency f_c /2^T +Nf_c /2^n+m.

Claims

1. A system for selectively generating any one of M signals frequency spaced apart of S Hz where S is a fixed value, and comprising:

first means for generating a first signal of frequency f_c ;

second means responsive to said first signal to produce a first binary output signal of frequency Nf_c /2ⁿ, where N is a variable integer and n is an integer;

first frequency divider means responsive to said first output signal to produce a second binary output signal of frequency Nf_c /2^n+m, where f_c /2^n+m =S and m is an integer;

second frequency divider means responsive to said first signal to produce a third binary output signal of frequency f_c /d, where d is an integer <

n+m; and

logic means responsive to said second and third binary output signal to produce a fourth output signal of average frequency f_c /d+Nf_c /2^n+m.

2. A system as in claim 1 in which said second means comprises an accumulator.

3. A system as in claim 1 in which said second means comprises a rate multiplier.

4. A system for selectively generating any one of M signals frequency spaced apart by S Hz where S is a fixed value, and comprising:

first means for generating a first signal of frequency f_c ;

second means responsive to said first signal to produce a first binary output signal of frequency Nf_c /2ⁿ

where N is a variable integer and n is an integer;

m stage binary counter means having an output terminal for the R most significant stages thereof and responsive to said first binary output signal to produce a second binary output signal of frequency Nf_c /2^n+m, where f_c /2^n+m =S and m is an integer;

T stage binary counter means having an output terminals for each stage thereof and responsive to said first signal to produce a third binary output signal of frequency f_c /2^T ; and

logic means responsive to said third binary output signal and to the binary signals appearing on the output terminals of the R most significant binary stages of said m stage binary counter means to produce a resultant output signal of average frequency f_c /2^T +Nf_c /2^n+m.

5. A system as in claim 4 in which said logic means comprises:

a T stage adder responsive to said third binary output signal and the contents of the Tth most significant bit positions of said m stage binary counter means to produce a fourth binary output signal of frequency f_c /2^T +Nf_c /2^n+m ;

a first plurality of XOR gates each having first and second input terminals and an output terminal;

means for supplying the contents of the most significant bit position of said T stage adder to the first input terminals of all of said first plurality of XOR gates; and

means for supplying the contents of descending orders of bit positions of said T stage adder, beginning with the next most significant bit position thereof, to the second input terminal of successive ones of said first plurality of XOR gates.

6. A system as in claim 5 in which said logic means further comprises:

a second plurality of XOR gates each having first and second input termminals and an output terminal;

means for supplying the contents of the most significant bit position of said T stage adder to the first input terminal of all of said second plurality of XOR gates;

means for supplying the contents of descending orders of bit positions of said m stage counter means, beginning with said Rth stage, to the second input terminals of successive ones of said second plurality of XOR gates; and

third means responsive to the output of said first and second plurality of XOR gates to produce said resultant output signal.

7. A system as in claim 4 in which said second means comprises an accumulator.

8. A system as in claim 4 in which said second means comprises a rate multiplier.

9. A system for selectively generating M signals frequency spaced apart by S Hz where S is a fixed value and comprising:

first means for generating a first signal of frequency f_c ;

second means responsive to said first signal to produce a first output signal of frequency Nf_c /2ⁿ, where N is a variable integer and n is an integer;

m stage binary counter means having an output terminal for the R most significant stages and responsive to said first output signal to produce a second output signal of frequency Nf_c /2^n+m =S and m is an integer;

T stage binary counter means for dividing said first signal by a factor 2^T and having an output terminal for each stage thereof;

T stage adder means responsive to the signals appearing on the output terminals of said T stage counter means and to the signals appearing on the output terminals of stages included in the R most significant stages of said m stage binary counter means to produce a digitized output signal of average frequency f_c /2^T +Nf_c /2^n+m ; and

logic means comprising digital-to-analog converting means responsive to the output signal from said T stage adder means and to the output signals appearing on the R^th to the Y^th output terminals of said m stage binary counter means to produce an analog signal of average frequency f_c /2^T +Nf_c /2^n+m, whereby Y≦

m.

10. A system as in claim 9 in which said logic means comprises:

a plurality of XOR gates each having first and second input terminals and an output terminal;

means for supplying the contents of the most significant bit position of said T stage adder means the first input terminal of all of said XOR gates;

means for supplying the contents of descending orders of bit positions of said T stage adder means, beginning with the next most significant bit position, to the second input terminals of successive ones of the next T-1 XOR gates;

means for supplying the contents of descending orders of bit positions of said m stage counter means, beginning with the R^th most significant bit position, to the second input terminals of successive ones of said plurality of XOR gates, beginning with the (R-1)^th XOR gate; and

in which said digital-to-analog converting means is responsive to the outputs of said plurality of XOR gates to produce said analog signal.