Time jitter determining apparatus

• US 4,350,879 A
• Filed: 10/29/1979
• Issued: 09/21/1982
• Est. Priority Date: 10/29/1979
• Status: Expired due to Term

• Current Assignee: University of Ottawa
• Original Assignee: Canadian Patents and Development Limited
• Inventors: Feher, Kamilo
• Primary Examiner(s): Thesz, Joseph M.
• Application Number:
  US06/089,585
• Time in Patent Office: 1,058 Days
• Field of Search: 235/92 PB, 235/92 EC, 235/92 CA, 235/92 MT, 235/92 PL, 235/92 T, 235/92 SH, 328/163, 328/162, 324/83 D, 371/68, 360/51
• US Class Current: 377/28
• CPC Class Codes: G01R 19/175 Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
• CPC Class Codes: G01R 25/005 Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
• CPC Class Codes: H04L 1/205 jitter monitoring

Abstract

The jitter determining apparatus uses only a jittery clock signal of period T_b recovered from the received data signal to determine peak to peak jitter J_pp and jitter distribution. The apparatus includes an AND gate having a pair of inputs. The inputs are coupled to a first signal which is the jittery clock signal delayed by a fixed amount nT_b where n is preferably greater than 5, and to a second signal which is a jittery pulse signal generated from the jittery clock signal. The second signal is also controllably delayed by a factor greater than twice the jitter J_pp. The AND gate produces output pulses when coincidence occurs between the two signals as the delay of the second signal is selectively varied. A counter counts the pulses for each selected delay position and thus provides the peak to peak time jitter J_pp of the clock signal.

Claims

1. Apparatus for determining time jitter of a clock signal of period T_b, recovered from a received data signal, comprising:

means for applying the clock signal to first and second signal paths;

signal delay means for delaying the signals in the signal paths relative to one another by a variable delay factor;

logic means coupled to the first and second signal paths for detecting coincidence of the relatively delayed clock signals, and

detector means coupled to the logic means for indicating the coincidence rate of the relatively delayed clock signals, as the delay is varied, whereby peak to peak time jitter is half of the relative shift of the delay between the point of minimum coincidence and the point of maximum coincidence.

2. Apparatus as claimed in claim 1 wherein the signal delay means includes:

fixed delay means having a fixed delay factor positioned in one of the signal paths; and

variable delay means having a variable delay factor positioned in one of the signal paths.

3. Apparatus as claimed in claim 2 wherein the fixed delay means is located in the first signal path and the variable delay means is located in the second signal path.

4. Apparatus as claimed in claim 2 or 3 wherein the fixed delay factor is nT_b where n is equal to or greater than 5.

5. Apparatus as claimed in claim 2 or 3 wherein the variable delay means delay factor varies over a period greater than 2J_pp where J_pp is the peak to peak time jitter of the recovered clock signal.

6. Apparatus as claimed in claim 3 wherein the second signal path further includes a pulse generating means for generating a signal consisting of a train of narrow pulses from the recovered clock signal.

7. Apparatus as claimed in claim 1 which further includes control means coupled to the signal delay means to increment the relative delay between the signal in the signal paths over the variable delay factor, in a predetermined sequence.

8. Apparatus for determining time jitter of a clock signal of period T_b, recovered from a received data signal, comprising:

means for applying the clock signal to first and second signal paths;

signal delay means for delaying the signals in the signal paths relative to one another by a variable delay factor;

AND gate means having one input coupled to the signal in the first signal path and one input coupled to the signal in the second signal path; and

counter means coupled to the AND gate means for counting the coincidence rate of pulses received from the AND gate, as the delay is varied.

9. Apparatus as claimed in claim 8 wherein the signal delay means includes:

fixed delay means having a fixed delay factor positioned to one of the signal paths; and

variable delay means having a variable delay factor positioned in one of the signal paths.

10. Apparatus as claimed in claim 9 wherein the fixed delay means is located in the first signal path and the variable delay means is located in the second signal path.

11. Apparatus as claimed in claim 9 or 10 wherein the fixed delay factor is nT_b where n is equal to or greater than 5.

12. Apparatus as claimed in claim 9 or 10 wherein the variable delay means delay factor varies over a period greater then 2J_pp where J_pp is the peak to peak time jitter of the recovered clock signal.

13. Apparatus as claimed in claim 10 wherein the second signal path further includes a pulse generating means for generating a signal consisting of a train of narrow pulses from the recovered clock signal.

14. Apparatus as claimed in claim 8 which further includes control means coupled to the signal delay means to increment the relative delay between the signal in the signal paths over the variable delay factor, in a predetermined sequence.