Combinational logic for generating gate drive signals for phase control rectifiers
First Claim
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1. In a phase-delay rectifier (PDR) having a silicon controlled rectifier (SCR) bridge circuit to transfer 3-phase line power to a dc link, wherein actual current in said link is compared with a current command for generating a firing angle control signal, α
- , applied to the PDR to produce a firing angle in a range from 0°
to 180°
, wherein the output voltage of the PDR is proportional to the cosine of the firing angle, and a cosine ramp signal for a given SCR relating to a given phase is used to generate the gate firing pulse for the SCR by comparing the difference signal, α
-control, to said cosine ramp to determine the correct time for firing each SCR, an improvement comprising means responsive to said control signal, cosine ramp signals and phase signals of said 3-phase line power transformed into 90°
phase delayed line neutral phase signals Aφ
, Bφ and
Cφ
for producing firing control signals, for SCR switches in said bridge circuit, said means comprisingmeans for comparing said phase signals Aφ
, Bφ and
Cφ
with each other in pairs for producing squarewave signals +Aφ
SYNC, +Bφ
SYNC and +Cφ
SYNC indicative of the 120°
phase relationship of the separate lines of said 3-phase power,means for generating said cosine ramp signals,comparator means for comparing said α
-control signal with each of said cosine ramp signals for generating a squarewave COMP signal from each of said cosine ramp signals that is high when said cosine ramp signals exceed said α
-control signal, andcombinational logic responsive to said COMP signals and said SYNC signals for producing said SCR firing control signals.
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Abstract
Control signals for phase-delay rectifiers, which require a variable firing angle that ranges from 0° to 180°, are derived from line-to-line 3-phase signals (φA, φB, φC) and both positive and negative firing angle control signals (+α and -α) which are generated by comparing (at 20) current command and actual current (sensed at 16). Line-to-line phases are transformed (32) into line-to-neutral phases and integrated (at 34) to produce 90° phase delayed signals (Aφ, Bφ, and Cφ) that are inverted (at 26a, b, c) to produce three cosine signals (C, A and B RAMP) such that for each its maximum occurs at the intersection of positive half cycles of the other two phases which are inputs to other inverters. At the same time, both positive and negative (inverted) phase sync signals are generated for each phase by comparing (at 27a, b, c) each with the next and producing a squarewave when it is greater. Ramp, sync and firing angle control signals are then used in combinational logic (FIG. 5) to generate the gate firing control signals for SCR gate drives (30) which fire SCR devices in a bridge circuit (24).
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Citations
12 Claims
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1. In a phase-delay rectifier (PDR) having a silicon controlled rectifier (SCR) bridge circuit to transfer 3-phase line power to a dc link, wherein actual current in said link is compared with a current command for generating a firing angle control signal, α
- , applied to the PDR to produce a firing angle in a range from 0°
to 180°
, wherein the output voltage of the PDR is proportional to the cosine of the firing angle, and a cosine ramp signal for a given SCR relating to a given phase is used to generate the gate firing pulse for the SCR by comparing the difference signal, α
-control, to said cosine ramp to determine the correct time for firing each SCR, an improvement comprising means responsive to said control signal, cosine ramp signals and phase signals of said 3-phase line power transformed into 90°
phase delayed line neutral phase signals Aφ
, Bφ and
Cφ
for producing firing control signals, for SCR switches in said bridge circuit, said means comprisingmeans for comparing said phase signals Aφ
, Bφ and
Cφ
with each other in pairs for producing squarewave signals +Aφ
SYNC, +Bφ
SYNC and +Cφ
SYNC indicative of the 120°
phase relationship of the separate lines of said 3-phase power,means for generating said cosine ramp signals, comparator means for comparing said α
-control signal with each of said cosine ramp signals for generating a squarewave COMP signal from each of said cosine ramp signals that is high when said cosine ramp signals exceed said α
-control signal, andcombinational logic responsive to said COMP signals and said SYNC signals for producing said SCR firing control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- , applied to the PDR to produce a firing angle in a range from 0°
-
9. In a phase-delay rectifier (PDR) having a silicon controlled rectifier (SCR) bridge circuit to transfer 3-phase line power to a dc link, wherein actual current in said link is compared with a current command for generating a firing angle control signal, α
- , applied to the PDR to produce a firing angle in a range from 0°
to 180°
, wherein the output voltage of the PDR is proportional to the cosine of the firing angle, and a cosine ramp signal for a given SCR relating to a given phase is used to generate the gate firing phase for the SCR by comparing the difference signal to said cosine ramp to determine the correct phase for firing each SCR, an improvement comprising combinatinal logic circuit responsive to said α
-control signal, cosine ramp signals and phase signals of said 3-phase line power transformed into 90°
phase delayed line neutral phase signals Aφ
, Bφ and
Cφ
for producing SCR firing control signals, said combinational logic circuit being defined by the logic equations;
space="preserve" listing-type="equation">FIRE A+=(A+·
B+)+(C+·
B+·
-Aφ
SYNC)
space="preserve" listing-type="equation">FIRE B+=(B+·
C+)+(C+·
A+·
-Bφ
SYNC)
space="preserve" listing-type="equation">FIRE C+=(C+·
A+)+(A+·
B+·
-Cφ
SYNC)where; -Aφ
SYNC=Cφ
>
Aφ-Bφ
SYNC=Aφ
>
Bφ-Cφ
SYNC=Bφ
>
CφA+=+Aφ
SYNC·
COMP-1B+=+Bφ
SYNC·
COMP-2C+=+Cφ
SYNC·
COMP-3and COMP 1=+α
control>
A RAMPCOMP 2=+α
control>
B RAMPCOMP 3=+α
control>
C RAMP - View Dependent Claims (10, 11, 12)
- , applied to the PDR to produce a firing angle in a range from 0°
Specification
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Current AssigneeCarlisle R. Dolland, Daniel W. Trimble, Lovelace Alan M Administrator of The National Aeronautics and Space Administration With Respect To An Invention of
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Original AssigneeCarlisle R. Dolland, Daniel W. Trimble, Lovelace Alan M Administrator of The National Aeronautics and Space Administration With Respect To An Invention of
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InventorsDolland, Carlisle R., Trimble, Daniel W., Lovelace, Alan M. Administrator of the National Aeronautics and space Administration, with respect to an invention of
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Primary Examiner(s)Shoop, William M.
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Application NumberUS06/280,154Time in Patent Office448 DaysField of Search318/803, 363/34, 363/37, 363/87, 363/129US Class Current363/87CPC Class CodesH02M 7/1626 with automatic control of t...
