Digital to analog converter having an analog to digital converter portion for an AC operation or a DC operation

• US 4,353,058 A
• Filed: 05/09/1980
• Issued: 10/05/1982
• Est. Priority Date: 05/09/1980
• Status: Expired due to Term

• Current Assignee: Singer PLC (Hayleys Plc)
• Original Assignee: Singer PLC (Hayleys Plc)
• Inventors: Sacks, Sidney M.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US06/148,118
• Time in Patent Office: 879 Days
• Field of Search: 340/347 M, 340/347 DA, 340/347 CC, 340/870.21
• US Class Current: 341/118
• CPC Class Codes: H03M 1/668 Servo-type converters

Abstract

A digital to analog converter is provided, for making a digital to analog conversion, and including, an analog to digital converter portion which may be an existing converter, an arithmetic logic unit which is coupled to the analog to digital converter portion, a digital to dc converter portion which is coupled to the arithmetic logic unit, an ac multiplex circuit for an ac operation which is adapted to be coupled to the digital to dc converter portion, a dc multiplex circuit for a dc operation which is adapted to be coupled to the digital to dc converter portion, a switch which couples either the ac multiplex circuit or the dc multiplex circuit to the digital to dc converter portion and which is coupled to and operated by the arithmetic logic unit, and a multiplex control which is actuated by the analog to digital converter portion and which is coupled to the ac multiplex circuit and to the dc multiplex circuit for controlling the output signals from the ac circuit and dc circuit to the analog to digital converter portion.

Claims

1. A digital to analog converter responsive to input digital command signals and including error compensation and being adapted to employ an analog to digital converter having an ac or dc mode of operation, comprising:

an arithmetic logic unit adapted to connect to the analog to digital converter, having a first input for receiving digital correction signals from the analog to digital converter for error compensation, and having a second input for receiving the input digital command signals,

a digital to dc converter portion coupled to the arithmetic logic unit, having an input for receiving corrected input digital command signals from the arithmetic logic unit, and

a multiplex circuit means coupled to the digital to dc converter portion and adapted to connect to the analog to digital converter, wherein the multiplex circuit means includes;

an ac multiplex circuit means having a plurality of ac channels and an ac multiplex unit for ac operation, and each channel of the ac multiplex circuit means includes a sample and hold amplifier, a capacitor coupled to the sample and hold amplifier, and a modulator assembly coupled to the sample and hold amplifier and coupled to the ac multiplex unit, said modulator assembly including a modular section and a filter section and a buffer section, and

a dc multiplex circuit means having a plurality of dc channels and a dc multiplex unit for dc operation, and each channel of the dc multiplex circuit means includes a sample and hold amplifier coupled to the dc multiplex unit, and a capacitor coupled to the sample and hold amplifier, and

said ac multiplex unit and said dc multiplex unit each being arranged to couple a selected channel of the ac multiplex circuit means or a selected channel of the dc multiplex circuit means to the analog to digital converter.

2. A digital to analog converter as claimed in claim 1, wherein:

the arithmetic logic unit includes switch means arranged to couple either the ac multiplex circuit means or the dc multiplex circuit means to the digital to dc converter portion, and

the arithmetic logic unit includes,

a microprocessor assembly and a program memory assembly arranged to control said digital to dc converter portion, wherein

said microprocessor assembly comprises, a microprocessor unit and a status decoder and a crystal oscillator, and is arranged to connect to a real time clock through a clock input line, and wherein

said program memory assembly comprises, a read only memory unit, a random access memory storage unit, an address storage and select unit, and a random access memory arbitor unit.