Solar cell junction processing system

• US 4,353,160 A
• Filed: 11/24/1980
• Issued: 10/12/1982
• Est. Priority Date: 11/24/1980
• Status: Expired due to Term

• Current Assignee: Spire Corporation
• Original Assignee: Spire Corporation
• Inventors: Little, Roger G., Armini, Anthony J.
• Primary Examiner(s): Weisstuch, Aaron
• Application Number:
  US06/209,542
• Time in Patent Office: 687 Days
• Field of Search: 29/572, 148/1.5, 136/258, 136/261, 136/290, 136/243, 250/492 A, 250/492 B
• US Class Current: 438/61
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1876 Particular processes or apparatus for batch treatment of the devices
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 438/907 Continuous processing

Abstract

An integrated system and process for the continuous formation of p-n junctions in solar cells in a cost-effective manner and under computer control. The integrated system essentially comprises an ion beam implanter, an electron beam annealer and a combination vacuum lock-and-wafer transport system, all disposed within a unitary housing maintained under a common vacuum environment.

The integrated system employs no wet chemistry operations and, is characterized by high reproducibility and narrow solar cell performance distribution.

Claims

1. An integrated dry junction processing system for solar cells comprising:

(a) a unitary housing provided with a solar cell input lock and a solar cell output lock;

(b) means for maintaining said housing under vacuum said means including a number of cryogenic pumps;

(c) continuous means including a combination vacuum lock-solar cell transport system and an ion beam implanter and a pulsed electron beam annealer for forming p-n junctions in solar cells within said housing, said pulsed electron beam annealer including a plurality of transmission line capacitors disposed circumferentially about a central horizontal axis;

(d) said housing featuring process controls for said ion beam implanter and said pulsed electron beam annealer and including an ion beam current integrator for implant dose control.

2. The integrated junction processing system of claim 1 wherein said continuous means includes computer control means.

3. The integrated junction processing system of claim 2 wherein said computer control means is a built-in microprocessor.

4. The integrated junction processing system of claim 1 wherein said ion beam current integrator is a digital current integrator.

5. The integrated junction processing system of claim 1 including cassette means for loading a plurality of said solar cells into said housing via said input lock and means for reloading the processed solar cells into cassettes in said output lock.

6. The integrated junction processing system of claim 1 wherein said ion beam implanter includes an ion source and a magnetic scanner to focus the ion beam of said implanter seriatim at said solar cells.

7. The integrated junction processing system of claim 1 further characterized in that said continuous means includes at least two parallel throughput lines, with each of said lines designed for forming p-n junctions in solar cells within said housing.

8. The integrated junction processing system of claim 7 wherein each of said throughput lines includes its separate ion beam implanter, its separate pulsed electron beam annealer, and its separate combination vacuum lock-solar cell transport system.

9. The integrated junction processing system of claim 7 further characterized in that said continuous means includes a built-in microprocessor.

10. A junction processing system for solar cells comprising:

(a) a housing;

(b) means for maintaining said housing under vacuum, said means including a number of cryogenic pumps;

(c) means for forming p-n junctions in solar cells within said housing, including an ion beam implanter and a pulsed electron beam annealer;

(d) said ion beam implanter including an ion source and a magnetic scanner to focus the ion beam of said implanter seriatim at said solar cells;

(e) said pulsed electron beam annealer including a plurality of transmission line capacitors disposed circumferentially about a central horizontal axis;

(f) means for transporting solar cells past said means for forming p-n junctions therein, said transporting means including a combination vacuum lock-solar cell transport system;

(g) computer means for operating said junction processing system;

(h) said housing provided with a solar cell input lock and a solar cell output lock forming a part of said transport system, with a plurality of said solar cells contained in cassette when introduced into said housing via said input lock, and being further characterized in that the processed solar cells are reloaded into cassettes in said output lock;

(i) said housing featuring process controls for said implanter and said annealer, said process controls including an ion beam current integrator for implant dose control.

11. The junction processing system of claim 10 wherein said computer means is a microprocessor.

12. The junction processing system of claim 10 further characterized in that said means for forming p-n junctions in solar cells is a continuous means and includes at least two parallel throughput lines.

13. The junction processing system of claim 12 wherein each of said throughput lines includes its separate ion beam implanter, its separate pulsed electron beam annealer, and its separate combination vacuum lock-solar cell transport system.

14. The junction processing system of claim 13 wherein two of said separate ion beam implanters have a common ion source.

15. The junction processing system of claim 10 wherein said ion beam current integrator is a digital current integrator.

16. A continuous, microprocessor-controlled process for the formation of p-n junctions in solar cells comprising:

(a) providing a plurality of semiconductor wafers integrally formed with one dopant material;

(b) loading a number of said wafers into cassettes;

(c) introducing said wafers with said cassettes via vacuum locks into a vacuum environment;

(d) removing said wafers from said cassettes and ion implanting said wafers within said vacuum environment with a second dopant material;

(e) annealing said ion implanted wafers by pulsing said wafers with an electron beam of an annealer including a plurality of transmission line capacitors;

(f) reloading said annealed wafers into cassettes; and

(g) removing said wafers with said cassettes via

vacuum locks from said vacuum environment.