Method for manufacture of a selective chemical sensitive FET transducer

• US 4,354,308 A
• Filed: 02/05/1980
• Issued: 10/19/1982
• Est. Priority Date: 11/04/1977
• Status: Expired due to Term

• Current Assignee: Kuraray Company Limited, Taoayuki Matsuo
• Original Assignee: Kuraray Company Limited, Taoayuki Matsuo
• Inventors: Esashi, Masayoshi, Shimada, Kiyoo, Matuo, Masayuki
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/118,774
• Time in Patent Office: 987 Days
• Field of Search: 29/569 R, 29/571, 29/583, 148/187, 204/195 B, 357/25
• US Class Current: 438/49
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

Abstract

A selective chemical sensitive field-effect transistor device for use in detection and measurement of chemical properties of substances to which the device is exposed is disclosed. The chemical sensitive FET device comprises a semiconductor substrate, at least one pair of spaced apart diffusion layers formed on one surface of the semiconductor substrate and forming source and drain regions, respectively, and a double layer structure consisting of a silicon oxide layer and an electrically insulating layer overlaying the silicon oxide layer. A gate region located on a portion of the surface of the semiconductor substrate between the diffusion layers is overlaid with a chemical selective membrane adapted to interact with certain substances. A method for the manufacture of the above described FET device is also disclosed.

Claims

1. A method for manufacturing a chemical selective field-effect transistor device, which comprises the steps of:

forming spaced apart diffusion layers on one surface of a semiconductor wafer made of silicon, said diffusion layers having a predetermined doping polarity opposite to that of the semiconductor wafer;

forming electroconductive channel stopper layers, one for each two of said diffusion layers, between the adjacent two of the diffusion layers except for one end portion of said diffusion layers and on said one surface of the semiconductor wafer, for avoiding formation of an electroconductive channel between said adjacent two of the diffusion layers, said channel stopper layer having a doping polarity opposite to that of the diffusion layers;

forming a cut-out portion in the semiconductor wafer so as to leave a substantially comb-shaped arrangement of elongated bodies of the semiconductor wafer in which said one end portion of the diffusion layers is located;

applying a layer of silicon dioxide over the entire surface area of the semiconductor wafer subsequent to the formation of the cut-out portion in the semiconductor wafer;

applying an electrically insulating layer sensitive to change in pH value and having an impermeability to a solution containing a particular chemical substance to which the device is exposed during measurement, over the silicon dioxide layer; and

trimming the semiconductor wafer along scribing lines, to provide separate chemical sensitive field-effect transistors.

2. A method for manufacturing a chemical selective field-effect transistor device as claimed in claim 1, wherein said electrically insulating layer having the impermeability to the solution is made of silicon nitride.

3. A method for manufacturing a chemical selective field-effect transistor device as claimed in claim 1, wherein said formation of the cut-out portion in the semiconductor wafer made of a single crystal of silicon includes the step of etching the silicon dioxide layer on the semiconductor wafer and the step of etching the semiconductor wafer.

4. A method for manufacturing a chemical selective field-effect transistor device as claimed in claim 3, wherein the etching of the semiconductor wafer is carried out by the use of an aqueous solution of amine.

5. A method for manufacturing a chemical selective field-effect transistor device as claimed in claim 1, wherein a gate region is defined between each adjacent two of the diffusion layers at a position adjacent the one end portion of said diffusion layers, and further comprising the step of applying a chemical selective membrane over a portion of the surface of the electrically insulating layer overlaying the gate region.