Data processor apparatus for multitariff meter
First Claim
1. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:
- timing means for generating periodic timing signals;
programmable data processor means including at least first and second signal storage files, and responsive to said timing signals for generating real time clock data stored in said first file;
readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;
said data processor means addressing said memory means and being programmed to retrieve said calendar time data stored at a location of said memory means addressed by said data processor means and store the data read-out in said second file;
said data processor means being further programmed to compare said real time clock data in said first file with said calendar time data in said second file, and, if the real time represented by the real time data exceeds the calendar time represented by the calendar time data, to cyclically increment the calendar time read-out by incrementing addresses of said memory means until the calendar time represented by the calendar time data read out of said memory means and stored in said second file is greater than the real time represented by the real time data stored in said first file.
2 Assignments
0 Petitions
Accused Products
Abstract
The meter includes a kilowatthour register which is continuously engaged as well as at least one special register (kilowatthour or demand) which is selectively engageable. A calendar memory (ROM) stores data representative of schedule events and the times (called "calendar times") at which such events are to be effected. The events may include the engagement of a special register or controlling a load under customer programming. A Central Processor Unit (CPU) deriving timing information from the line frequency generates real time data and compares it with the stored calendar time for implementation of a schedule event. When the schedule event time arrives, the CPU implements the event (as by energizing an appropriate register selection circuit) and addresses the next schedule event in the calendar memory. The system includes a display for the real time data as well as means for setting the time data. In the event of a power outage, a battery carryover is provided, in which case, the CPU generates the real time data from its crystal clock and causes the system to enter a power conservation mode in which the display is disabled and the special registers cannot be engaged. The CPU re-initializes itself with the next schedule event whenever the time is set, or the calendar memory is removed, or the real time clock "rolls over" at midnight, or when AC power is re-established following a power outage.
-
Citations
15 Claims
-
1. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:
- timing means for generating periodic timing signals;
programmable data processor means including at least first and second signal storage files, and responsive to said timing signals for generating real time clock data stored in said first file;
readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;
said data processor means addressing said memory means and being programmed to retrieve said calendar time data stored at a location of said memory means addressed by said data processor means and store the data read-out in said second file;
said data processor means being further programmed to compare said real time clock data in said first file with said calendar time data in said second file, and, if the real time represented by the real time data exceeds the calendar time represented by the calendar time data, to cyclically increment the calendar time read-out by incrementing addresses of said memory means until the calendar time represented by the calendar time data read out of said memory means and stored in said second file is greater than the real time represented by the real time data stored in said first file. - View Dependent Claims (2, 14, 15)
- timing means for generating periodic timing signals;
-
3. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:
- timing means for generating periodic timing signals;
programmable data processor means including at least a real time signal storage file and a calendar time signal storage file, said data processor means being responsive to said timing signals for generating real time clock data stored in said real time file;
readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;
said data processor means addressing said memory means and being programmed to retrieve said calendar time data therefrom and store the same in said calendar time file;
said data processor means being further programmed to compare said real time clock data in said real time file with said calendar time data in said calendar time file for effecting a schedule event, and said data processor means being programmed to reset said calendar time file to zero when the contents of said real time file reaches a predetermined time, and to then cyclically increment said calendar times by incrementing addresses of said memory means until calendar time data in said calendar time file is greater than real time data stored in said real time file, thereby reinitializing the system.
- timing means for generating periodic timing signals;
-
4. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:
- timing means for generating periodic timing signals;
programmable data processor means including at least a real time signal storage file, and a calendar time signal storage file, said data processor means being responsive to said timing signals for generating real time clock data stored in said first file;
readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;
said data processor means addressing said memory means and being programmed to retrieve said calendar time data therefrom and store the same in said second file;
said data processor means being further programmed to compare said real time clock data in said first file with said calendar time data in said second file, and to cyclically increment said calendar times by incrementing addresses of said memory means until calendar time data in said second file is greater than real time data stored in said first file, and said data processor means being responsive to the disconnecting of said memory means for communication with said data processor means for resetting the contents of said calendar time file to zero when said memory means is disconnected therefrom and thereby cause said data processor to re-initialize itself with said memory means by loading the data into said second file representative of the next schedule event.
- timing means for generating periodic timing signals;
-
5. Apparatus for applying predetermined switching schedules in a load control system for controllably switching a load to and from a source of electrical power, the combination comprising:
- a source of timing signals;
programmable data processor means responsive to said source of timing signals for generating real time clock data and storing the same in a first file;
memory means for storing calendar data representative of calendar times for effecting schedule events and event data associated with said calendar data, said calendar data including at least first and second dates defining seasonal changes for a given year, and at least first and second switching schedules to be applied, said data processor being in communication with said memory means and programmed to retrieve calendar data therefrom for comparing said calendar data with said real time data and for effecting said schedule events in accordance with said event data when real time equals the next-occurring calendar time, and for sequencing said calendar time data when a schedule event has been effected. - View Dependent Claims (6, 7, 8)
- a source of timing signals;
-
9. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:
- programmable data processor means including timing source means for generating real time data and for storing the same in a real time file, and including a calendar time file;
at least first and second interchangeable memory means, one of said memory means comprising calendar memory means for storing data representative of calendar times and associated schedule events, and the other memory means comprising a source of real time data for loading said real time file of said data processor means, each memory means having associated with it an identifying data signal, said data processor means being programmed to retrieve calendar times from one of said memories and storing the same in said calendar time file, and being further programmed to define said identifying data signals of said respective memory means and being responsive to the absence of an identifying data signal for resetting said calendar time file to zero, said data processor means being responsive to the data signal identifying a calendar memory means for comparing the contents of said real time file with the contents of said calendar time file from said calendar memory and for effecting said schedule event when said real time equals to said calendar time, and for then incrementing said calendar time to the next occurring calendar time. - View Dependent Claims (10, 11, 12)
- programmable data processor means including timing source means for generating real time data and for storing the same in a real time file, and including a calendar time file;
-
13. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:
- external timing circuit means receiving line frequency voltage for generating a signal each cycle of line frequency;
countdown circuit means responsive to said line frequency signal for generating digital output signal for each predetermined number of said line frequency signals;
programmable data processor means responsive to the output signal of said countdown circuit means for generating real time data therefrom and for storing the same in a first file;
memory means for storing data representative of calendar times for effecting schedule events and for storing associated event data;
said data processor means being programmed to periodically compare said real time data with said calendar time data from said memory means for implementing said event data when real time equals the next scheduled calendar time, said program including predetermined delays comprising a substantial portion of a period of the output signals from said countdown counter circuit means during which said data processor means is not responsive to said external timing signals, whereby said system is rendered less sensitive to noise, on said line frequency signal.
- external timing circuit means receiving line frequency voltage for generating a signal each cycle of line frequency;
Specification