Data processor apparatus for multitariff meter

• US 4,355,361 A
• Filed: 02/06/1980
• Issued: 10/19/1982
• Est. Priority Date: 02/06/1980
• Status: Expired due to Term

• Current Assignee: Schlumberger Resource Management Services Incorporated (Schlumberger NV)
• Original Assignee: Sangamo Weston, Inc. (Atos SE)
• Inventors: Coppola, Richard G., Riggs, Richard L.
• Primary Examiner(s): Krass, Errol A.
• Application Number:
  US06/119,071
• Time in Patent Office: 986 Days
• Field of Search: 364/483, 364/464, 364/492, 364/493, 364/900, 324/103 R, 324/113, 235/92 EL, 235/92 CA
• US Class Current: 713/600
• CPC Class Codes: G01R 21/1333 adapted for special tariff measuring

Abstract

The meter includes a kilowatthour register which is continuously engaged as well as at least one special register (kilowatthour or demand) which is selectively engageable. A calendar memory (ROM) stores data representative of schedule events and the times (called "calendar times") at which such events are to be effected. The events may include the engagement of a special register or controlling a load under customer programming. A Central Processor Unit (CPU) deriving timing information from the line frequency generates real time data and compares it with the stored calendar time for implementation of a schedule event. When the schedule event time arrives, the CPU implements the event (as by energizing an appropriate register selection circuit) and addresses the next schedule event in the calendar memory. The system includes a display for the real time data as well as means for setting the time data. In the event of a power outage, a battery carryover is provided, in which case, the CPU generates the real time data from its crystal clock and causes the system to enter a power conservation mode in which the display is disabled and the special registers cannot be engaged. The CPU re-initializes itself with the next schedule event whenever the time is set, or the calendar memory is removed, or the real time clock "rolls over" at midnight, or when AC power is re-established following a power outage.

Claims

1. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:

timing means for generating periodic timing signals;

programmable data processor means including at least first and second signal storage files, and responsive to said timing signals for generating real time clock data stored in said first file;

readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;

said data processor means addressing said memory means and being programmed to retrieve said calendar time data stored at a location of said memory means addressed by said data processor means and store the data read-out in said second file;

said data processor means being further programmed to compare said real time clock data in said first file with said calendar time data in said second file, and, if the real time represented by the real time data exceeds the calendar time represented by the calendar time data, to cyclically increment the calendar time read-out by incrementing addresses of said memory means until the calendar time represented by the calendar time data read out of said memory means and stored in said second file is greater than the real time represented by the real time data stored in said first file.

2. The apparatus of claim 1 wherein said first and second files comprise real time and calendar time files respectively, said apparatus further comprising external means for setting the contents of real time file, said data processor means being responsive to the setting of said real time file for resetting the contents of said calendar time file to contain data representative of a future event.

14. The apparatus according to any one of claims 1, 5, 9, or 13 comprising an electric meter system for measuring the consumption of electric power, the system including at least first and second selectively engageable rate indicating registers, said system further comprising first and second register selection circuits associated respectively with said first and second registers and responsive to first and second outputs from said data processor means, said data processor means being responsive to said event data for selectively energizing said register selection circuits when indicated by the calendar time data retrieved being equal to the contents of said real time file and the event data associated therewith being representative of engaging one of said registers.

15. The apparatus of claim 14 wherein said data processor means includes a third output, said data processor means selectively energizing said third output at a preselected time as determined by a calendar word from said memory means and associated event data.

3. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:

timing means for generating periodic timing signals;

programmable data processor means including at least a real time signal storage file and a calendar time signal storage file, said data processor means being responsive to said timing signals for generating real time clock data stored in said real time file;

readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;

said data processor means addressing said memory means and being programmed to retrieve said calendar time data therefrom and store the same in said calendar time file;

said data processor means being further programmed to compare said real time clock data in said real time file with said calendar time data in said calendar time file for effecting a schedule event, and said data processor means being programmed to reset said calendar time file to zero when the contents of said real time file reaches a predetermined time, and to then cyclically increment said calendar times by incrementing addresses of said memory means until calendar time data in said calendar time file is greater than real time data stored in said real time file, thereby reinitializing the system.

4. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:

timing means for generating periodic timing signals;

programmable data processor means including at least a real time signal storage file, and a calendar time signal storage file, said data processor means being responsive to said timing signals for generating real time clock data stored in said first file;

readable memory means for storing data representative of a plurality of calendar times for effecting schedule events;

said data processor means addressing said memory means and being programmed to retrieve said calendar time data therefrom and store the same in said second file;

said data processor means being further programmed to compare said real time clock data in said first file with said calendar time data in said second file, and to cyclically increment said calendar times by incrementing addresses of said memory means until calendar time data in said second file is greater than real time data stored in said first file, and said data processor means being responsive to the disconnecting of said memory means for communication with said data processor means for resetting the contents of said calendar time file to zero when said memory means is disconnected therefrom and thereby cause said data processor to re-initialize itself with said memory means by loading the data into said second file representative of the next schedule event.

5. Apparatus for applying predetermined switching schedules in a load control system for controllably switching a load to and from a source of electrical power, the combination comprising:

a source of timing signals;

programmable data processor means responsive to said source of timing signals for generating real time clock data and storing the same in a first file;

memory means for storing calendar data representative of calendar times for effecting schedule events and event data associated with said calendar data, said calendar data including at least first and second dates defining seasonal changes for a given year, and at least first and second switching schedules to be applied, said data processor being in communication with said memory means and programmed to retrieve calendar data therefrom for comparing said calendar data with said real time data and for effecting said schedule events in accordance with said event data when real time equals the next-occurring calendar time, and for sequencing said calendar time data when a schedule event has been effected.

6. The apparatus of claim 5 further comprising display means for visually displaying data;

display driver circuit means responsive to outputs from said data processor means for selectively energizing said display means to display data from said data processor means;

display selection switch means;

display set switch means;

said data processor means being programmed to cyclically sense the state of said selection switch means and said set switch means for transmitting data to said display driver circuit means, the data transmitted to said display driver circuit means comprising time words representative of different portions of real time data in response to the sequential actuation of said display selection switch means, said data processor means being further responsive to the actuation of said display set switch means for incrementing the contents of a time word selected by said display selection switch means.

7. The apparatus of claim 6 further comprising multiplexer circuit means for selectively communicating said data processor means with said display selection switch means and said display set switch means, said source of timing signals comprising counter circuit means responsive to a line frequency timing signal for counting down the repetition rate of said line frequency timing signal to generate said timing signals, said multiplexer circuit means being responsive to the output of said counter circuit means for communicating said data processor means with said counter circuit means to extend said timing signals to said data processor means, said data processor means being responsive to said timing signals for generating said data in said first file, which comprises a real time data file, representative of real time.

8. The apparatus of claim 7 further comprising crystal oscillator means for generating a clock signal for said data processor means, said data processor means being responsive to the absence of said line frequency timing signal for using said clock signal of said crystal oscillator means to increment the contents of said real time data file.

9. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:

programmable data processor means including timing source means for generating real time data and for storing the same in a real time file, and including a calendar time file;

at least first and second interchangeable memory means, one of said memory means comprising calendar memory means for storing data representative of calendar times and associated schedule events, and the other memory means comprising a source of real time data for loading said real time file of said data processor means, each memory means having associated with it an identifying data signal, said data processor means being programmed to retrieve calendar times from one of said memories and storing the same in said calendar time file, and being further programmed to define said identifying data signals of said respective memory means and being responsive to the absence of an identifying data signal for resetting said calendar time file to zero, said data processor means being responsive to the data signal identifying a calendar memory means for comparing the contents of said real time file with the contents of said calendar time file from said calendar memory and for effecting said schedule event when said real time equals to said calendar time, and for then incrementing said calendar time to the next occurring calendar time.

10. The apparatus of claim 9 wherein said second memory means is removably associated with said data processor means, and upon connection of said second memory means to said data processor means, said data processor means is further responsive to the data signal identifying said second memory means for periodically transferring the contents of said calendar time file to said real time file, and for transferring real time data from said second memory means to said calendar time file, whereby when said second memory means is disconnected from said data processor means, the contents of said real time file will be representative of real time.

11. The apparatus of claim 10 wherein calendar time data and associated schedule event data are stored in locations of said calendar memory means in chronological order for sequential addresses, and said data processor means is further responsive to the absence of an identifying data signal to reset the contents of said calendar time file to zero, and is responsive to the identifying data provided when said calendar memory means is subsequently connected to said data processor means to compare the contents of said real time file with the contents of said calendar time file and sequentially increment the address of said calendar memory means until a location of said calendar file is reached which stores calendar data representing a time greater than the real time indicated by the contents of said real time file.

12. The apparatus of claim 11 further comprising an external source of timing signals derived from a line frequency voltage, said data processor means being responsive to said external source of timing signals for generating real time data in said real time file, said system further including a battery, and battery carryover circuit means for supplying power from said battery to said data processor means if said external source of power is removed, whereby said data processor circuit means may be set by said second memory means without an external power source and transported to an installation site, and said battery and battery carryover means will maintain power to said data processor circuit means for keeping real time current until an external source of power is applied.

13. In a system for controllably switching a load to and from a source of electrical power according to a predetermined time schedule, the combination comprising:

external timing circuit means receiving line frequency voltage for generating a signal each cycle of line frequency;

countdown circuit means responsive to said line frequency signal for generating digital output signal for each predetermined number of said line frequency signals;

programmable data processor means responsive to the output signal of said countdown circuit means for generating real time data therefrom and for storing the same in a first file;

memory means for storing data representative of calendar times for effecting schedule events and for storing associated event data;

said data processor means being programmed to periodically compare said real time data with said calendar time data from said memory means for implementing said event data when real time equals the next scheduled calendar time, said program including predetermined delays comprising a substantial portion of a period of the output signals from said countdown counter circuit means during which said data processor means is not responsive to said external timing signals, whereby said system is rendered less sensitive to noise, on said line frequency signal.