Apparatus and method for utilizing partially defective memory devices
First Claim
1. A mapping system to permit use of a group of partially defective memory devices as a memory unit, each of said partially defective memory devices characterized as having all of its respective faults within a contiguous address space, said mapping system comprising:
- mapping memory means for storing data which would be stored in the defective areas of said group of partially defective memory devices if said group of partially defective memory devices were faultfree;
detection means, coupled to the address input lines to said memory unit, said detection means for detecting when an access is directed to the defective area of one of said group of partially defective memory devices;
enabling means, connected to said group of partially defective memory devices and responsive to said detection means, said enabling means for selectively enabling accesses to said group of partially defective memory devices or said mapping memory means; and
redirect means, coupled to the address input lines to said memory unit and responsive to said detection means, said redirect means for redirecting an access to one of said defective areas to a corresponding mapping storage area in said mapping memory means, said redirect means including multiplexor means, responsive to an indicated access to said mapping memory means, said multiplexor means for replacing information on a subset of the address input lines to said mapping memory means.
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Accused Products
Abstract
An apparatus and method of utilizing a group of partially defective memory devices in conjunction with a single faultfree memory device to form an effectively faultfree memory unit. Each of the partial devices and the faultfree device are characterized as requiring an address input to be presented in two segments at separate times during an access cycle. Each of the partial devices is characterized as having all of its respective faults within a contiguous address space, the group of partial devices configured to form one continuous addressable storage area. The first segment of the input address is presented to the group of partial devices and the faultfree device, and then a first stage access is initiated to all devices. Concurrently, the second segment of the input address is compared with the address combination which defines the faulty areas of the partial devices being accessed. If a match is obtained, the second segment of the input address is modified to specify an address in a portion of the faultfree device allocated for the corresponding partial device, and a second stage access is initiated to the faultfree device. If a match is not obtained, a second stage access is initiated to the group of partial devices utilizing the second segment of the unmodified input address.
176 Citations
24 Claims
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1. A mapping system to permit use of a group of partially defective memory devices as a memory unit, each of said partially defective memory devices characterized as having all of its respective faults within a contiguous address space, said mapping system comprising:
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mapping memory means for storing data which would be stored in the defective areas of said group of partially defective memory devices if said group of partially defective memory devices were faultfree; detection means, coupled to the address input lines to said memory unit, said detection means for detecting when an access is directed to the defective area of one of said group of partially defective memory devices; enabling means, connected to said group of partially defective memory devices and responsive to said detection means, said enabling means for selectively enabling accesses to said group of partially defective memory devices or said mapping memory means; and redirect means, coupled to the address input lines to said memory unit and responsive to said detection means, said redirect means for redirecting an access to one of said defective areas to a corresponding mapping storage area in said mapping memory means, said redirect means including multiplexor means, responsive to an indicated access to said mapping memory means, said multiplexor means for replacing information on a subset of the address input lines to said mapping memory means. - View Dependent Claims (2, 3, 4)
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5. A mapping system to permit use of a group of partially defective memory devices as a memory unit, each of said partial devices characterized as requiring the address of any location to be presented in at least two segments at separate times during a partial device address cycle, each of said partial devices further characterized as having all of its respective faults within a contiguous address space, said group of partial devices configured to form one continuous storage area, said mapping system comprising:
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mapping memory means for storing data which would be stored in the defective areas of said group of partial devices if said group of partial devices were faultfree, said mapping memory means characterized as requiring the address of any location to be presented in a least two segments at separate times during an access cycle to said mapping memory means, the first and second segments of both the mapping memory means address and the partial device address presented during first and second stages of a memory unit access, respectively; detection means, coupled to the address input lines to said memory unit, said detection means for detecting when an access is directed to the defective area of one of said partial devices, said detection means including partial definition storage means for storing information indicating the addresses of the defective areas in the group of partial devices, and compare means, connected to said partial definition storage means and responsive to the first stage of a memory unit access, said compare means for comparing portions of the address of the location to be accessed with information in said partial definition storage means; and enabling means, connected to said group of partial devices and responsive to said detection means, said enabling means for selectively enabling or disabling accesses to said group of partial devices or said mapping memory means. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of utilizing a group of partially defective memory devices in conjunction with a single faultfree memory device to form an effectively faultfree memory unit, each of said partial devices and said faultfree device characterized as requiring an address input to be presented in at least two segments at separate times during an access cycle, each of said partial devices characterized as having all of its respective faults within a contiguous address space, said group of partial devices configured to form one continuous addressable storage area, said method comprising the steps of:
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a. presenting the first segment of the address of the location to be accessed to said group of partial devices and to said faultfree device and then initating a first stage access to said group of partial devices and to said faultfree device; b. concurrent with said step a, comparing the second segment of the address of the location to be accessed with address information which identifies the faulty areas of the partial devices being accessed; c. if a match is obtained in said step b, c1. modifying the second segment of the address of the location to be accessed to specify an address in a portion of the faultfree device allocated for the corresponding partial device, and c2. presenting the modified second segment of the address of the location to be accessed to the faultfree device; and d. if a match is not obtained in said step b, d1. presenting the unmodified second segment of the address of the location to be accessed to the group of partial devices. - View Dependent Claims (21, 22, 23, 24)
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Specification