Offset compensating circuit for operational amplifier

• US 4,356,450 A
• Filed: 11/17/1980
• Issued: 10/26/1982
• Est. Priority Date: 11/29/1979
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Masuda, Eiji
• Primary Examiner(s): Mullins, James B.
• Assistant Examiner(s): Wan, Gene
• Application Number:
  US06/207,731
• Time in Patent Office: 708 Days
• Field of Search: 330/9, 330/259, 330/290
• US Class Current: 330/9
• CPC Class Codes: H03F 1/304 and using digital means

Abstract

Disclosed is an offset compensating circuit for an operational amplifier having its noninverting input terminal supplied with a compensating voltage corresponding to its output voltage obtained when its inverting input terminal is grounded. This offset compensating circuit includes a comparator connected to the output terminal of the operational amplifier and comparing the output voltage of the operational amplifier with a set voltage to deliver a binary signal corresponding to the result of such comparison, a pulse generator, an up-down counter for counting output pulses from the pulse generator in a count direction in accordance with the level of the output signal of the comparator, and a D/A converter for supplying the noninverting input terminal of the operational amplifier with a voltage corresponding to the count output of the up-down counter.

Claims

1. An offset compensating circuit for an operational amplifier having two input terminals comprising:

a reference voltage terminal connectable to a first input terminal;

comparing means connected to the output terminal of said operational amplifier and to said reference voltage terminal for comparing signal levels at both said terminals and generating a two-level signal indicating the result of said comparison;

counting means connected to said comparing means for generating a digital count at an output terminal in response to the state of said two-level signal; and

a digital-to-analog converter having an input terminal connected to the output terminal of said counting means and and having an output terminal connected to a second input terminal of said operational amplifier to supply said operational amplifier with an analog signal corresponding to said count to compensate for voltage offset in said operational amplifier.

2. An offset compensating circuit according to claim 1, wherein said counting means includes a pulse generator and an up-down counter for counting output pulses from said pulse generator in a count direction determined by the state of said two-level signal.

3. An offset compensating circuit according to claim 1, further comprising a switching circuit for generating a start signal and a stop signal, and a switch whose first movable contact is connected to said reference voltage terminal, whose second movable contact is connected to a signal input terminal, and whose fixed contact is connected to said first input terminal of said operational amplifier, so that said first and second movable contacts may be connected with said fixed contact in response to said start and stop signals, respectively.

4. An offset compensating circuit according to claim 3, wherein said switching circuit is formed of a flip-flop and delivers said start and stop signals when set and reset, respectively.

5. An offset compensating circuit according to claim 4, wherein said flip-flop is set in response to a signal resulting from the turning on of a power source.

6. An offset compensating circuit according to claim 4, wherein said flip-flop is set in response to a closing of a set switch connected between the set terminal of a flip-flop and said power source.

7. An offset compensating circuit according to claim 5 or 6, wherein said counting means includes a pulse generating circuit energizing in response to said start signal to supply a first pulse signal to the reset terminal of said flip-flop after a given period of time and, for said given period of time, to supply a second pulse signal and a third pulse signal the width of pulses of said third pulse signal being shorter than those of said second pulse signal, an AND gate having as inputs the output signal of said comparing means and said third pulse signal, and an up-down counter having a reset terminal supplied with said stop signal, a count direction control terminal supplied with an output signal from said AND gate and an input terminal supplied with said second pulse signal, whereby said counter counts the pulses of said second pulse signal.

8. An offset compensating circuit according to claim 7, wherein said pulse generating circuit is de-energized in response to a change of the output signal of said comparing means to stop the generation of said first, second and third pulse signals.

9. An offset compensating circuit according to claim 8, wherein the output terminal of said operational amplifier is connected to one input terminal of said operational amplifier through a switch which is closed and opened in response to said start and stop signals, respectively.

10. An offset compensating circuit comprising:

a reference voltage terminal;

an operational amplifier having two input terminals, a first one of which is connected to receive a signal from said reference voltage terminals;

comparing means having a first input terminal connected with the output terminal of said operational amplifier, having a second input connected to a comparison signal, said comparing means generating a two-level signal at an output terminal;

computing means connected to the output terminal of said comparing means to deliver first and second digital signals at first and second output terminals, respectively, in response to the state of said two-level signal;

a first D/A converter connected between the first output terminal of said computing means and the second input terminal of said comparing means to supply the second input terminal of said comparing means with said comparison signal corresponding to an output signal of said computing means; and

a second D/A converter connected between the second output terminal of said computing means and a second input terminal of said operational amplifier to supply said operational amplifier with an analog signal corresponding to a second output signal of said computing means to compensate for voltage offset in said operational amplifier.