Video extractor

• US 4,357,607 A
• Filed: 02/01/1980
• Issued: 11/02/1982
• Est. Priority Date: 02/09/1979
• Status: Expired due to Term

• Current Assignee: Hollandse Signaalapparaten BV (Thales SA)
• Original Assignee: Hollandse Signaalapparaten BV (Thales SA)
• Inventors: Van der Heijden, Wilhelmus F., Intres, Edward L.
• Primary Examiner(s): Tubbesing, T. H.
• Application Number:
  US06/117,681
• Time in Patent Office: 1,005 Days
• Field of Search: 343/5 PD, 343/5 VQ
• US Class Current: 342/197
• CPC Class Codes: G01S 7/2923 based on data belonging to a number of consecutive radar periods
• CPC Class Codes: G01S 7/2927 by deriving and controlling a threshold value
• CPC Class Codes: G01S 7/295 Means for transforming co-ordinates or for evaluating data, e.g. using computers
• CPC Class Codes: G06F 17/18 for evaluating statistical data , e.g. average values, frequency distributions, probability functions, regression analysis forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04

Abstract

A video extractor for use in a pulse radar apparatus comprises a shift-register memory for storing a number of words, each of which containing the information about the target position and size, as established for each of the range quants in which the desired range interval is divided. The video extractor thereto contains a range counter, whose counting rate is equal to the rate at which said words are shifted into the memory. An arithmetic unit receives the words shifted out of the memory and, in response to the video and angular data from the pulse radar apparatus and to the range data provided by the range counter, updates if necessary all information contained in said words with each successive range sweep. Because all information referring to one target has to be concentrated in a single word the arithmetic unit transfers the updated information to following or preceding words fetched from the memory. A readout circuit connected to the arithmetic unit and to the range counter is used to read out the information referring to the particular target.

Claims

1. A video extractor for use in a pulse radar apparatus, comprising:

A. a shift-register memory, which is capable of storing a number of words corresponding with the number of range quants dividing the range interval to be covered by the pulse radar apparatus, said words containing information describing the number of hits received in a range quant, the number of misses established in a range quant, the initial and the final azimuth values of a target, the number of range quants in which the hits contributing to the buildup of a target have been recorded, the initial range of a target, and the status of various control bits for each range quant, said control bits including;

a. a recording bit (R bit), indicating that a new echo is applied to the video extractor in a certain range quant;

b. a detection bit (D bit), indicating that in a certain range quant a minimum number of hits have been recorded;

c. an identification bit (H bit), indicating the word in which the data to be determined is concentrated;

d. a miss bit (M bit), indicating that in a certain range quant no hits have been recorded; and

e. a readout bit (U bit), indicating that the word associated with a certain range quant can be read out;

B. a range counter whose counting rate is equal to the rate at which said words are shifted in the memory;

C. an arithmetic unit, comprising;

a. a hit counter for recording the number of hits received in a range quant;

b. a miss counter for recording the number of misses established in a range quant;

c. a circuit for determining the initial and the final azimuth values of a target;

d. a range interval counting unit for determining the number of range quants in which the hits contributing to the buildup of a target have been recorded;

e. a circuit for determining the initial range of a target;

f. control bit recording means for recording the status of the various control bits for each range quant;

said arithmetic unit receiving the words shifted out of memory and, in response to video and angular data received from the pulse radar apparatus and to range data provided by the range counter, updating information contained in said words during successive range sweeps and effecting concentration of information referring to each target in a single word by transferring the updated information to following or preceding words fetched from memory;

D. a central control unit generating control signals which together with the control bits controls the counters and circuits of the arithmetic unit; and

E. a readout circuit adapted to read out target position, size and range information from the words and to read out target range information from the range counter.

2. A video extractor as in claim 1, wherein the hit counter comprises a first and a second register and an adder circuit, whereby the hit counts fetched from memory for the successive range quants and contained in the corresponding words are transferred to the first and the second registers, incremented by 1 in the adder circuit if a hit has been recorded in the respective range quant, and shifted back into the memory.

3. A video extractor as in claim 2, wherein the hit counter comprises a first comparator for comparing the recorded number of hits with a preset detection criterion and, if said criterion has been met, adapting the status of the D bit accordingly.

4. A video extractor as in claim 3, wherein the hit counter comprises a second comparator for comparing the recorded number of hits with a preset maximum length criterion, and if said maximum length criterion has been met, effecting delivery of a signal to the readout circuit to block the readout of the word containing the respective hit count.

5. A video extractor as in claim 2, wherein the hit counter comprises a modification circuit, including a comparator for indicating whether the contents of the first register are larger or smaller than the contents of the second register, and further including a logic circuit which, in response to said indication provided by said comparator, makes the contents of the two registers equal to each other when the minimum number of hits is recorded in the range quants of which the hit counts are contained in the two registers.

6. A video extractor as in claim 1, wherein the miss counter comprises a first and a second register, a counting control circuit, and a counting circuit controlled by said counting control circuit, whereby the miss counts fetched from memory for the successive range quants and contained in the corresponding words are transferred to the first and the second registers, incremented by 1 in said counting circuit if said counting control circuit establishes a miss in the respective range quant after the recording of hits, and shifted back into the memory.

7. A video extractor as in claim 6, wherein the miss counter comprises a comparing circuit for comparing the recorded number of misses with a present miss criterion and, if said miss criterion has been met, adapting the status of the M bit accordingly.

8. A video extractor as in claim 6, wherein the counting control circuit comprises means for applying a signal to the counting circuit effecting decrementing of the miss count by 1, for a certain range quant, if a hit is recorded for that quant while the existing hit count therefor is other than zero.

9. A video extractor as in claim 8, wherein the miss counter comprises a resetting circuit, including a logic circuit and a switch controlled by this logic circuit, whereby at the instant a detection criterion is met the logic circuit controlling the switch causes switch to shift the zero-set miss count back into the memory.

10. A video extractor as in claim 8, wherein the miss counter comprises a resetting circuit including a logic circuit and a switch controlled by this logic circuit, whereby, if in a certain range quant a hit is recorded while the hit count for said certain range quant is already other than zero or is other than zero at the instant of meeting a detection criterion, the logic circuit controlling the switch causes the switch to shift the zero-set miss count back into the memory.

11. A video extractor as in claim 1, wherein the circuit for determining the initial and final azimuth values of a target comprises a first and a second register, an azimuth control circuit and a first switch controlled by said azimuth control circuit, whereby, as soon as a new echo is established in a certain range quant, said azimuth control circuit acts on said first switch to pass the instantaneous antenna azimuth value, applied to the video extractor, to the memory, and whereby the initial azimuth values fetched from memory for the successive range quants and contained in the corresponding words are shifted through the first and the second registers successively, and are then returned to the memory via said first switch only if said first switch is not in the position in which the instantaneous antenna azimuth value is passed to the memory.

12. A video extractor as in claim 11, wherein the circuit for determining the initial and final azimuth values of a target comprises a third and a fourth register and a second switch controlled by the azimuth control circuit, whereby as soon as a hit is recorded in a range quant identified by the H bit, after meeting a detection criterion, the logic circuit acts on said second switch to pass the instantaneous antenna azimuth value, applied to the video extractor, to the memory in each radar sweep until establishing the end of the echo, and whereby the final azimuth values fetched from memory for the successive range quants and contained in the corresponding words are shifted through the third and the fourth registers successively, and are then returned to the memory via said second switch only if said second switch is not in the position in which the instantaneous antenna azimuth value is passed to the memory.

13. A video extractor as in claim 12, wherein the azimuth control circuit comprises a comparator for indicating whether the contents of the first register are larger or smaller than the contents of the second register, and a conditional circuit, which responds to data supplied by the comparator, to the 180°

bits of the azimuth values contained in said four registers, and to the H bits of the range quants of which the initial azimuth values are contained in the respective registers, by equalizing, in case two echoes merge into one new hit cluster, the initial azimuth value of the hit cluster so produced and the initial azimuth value contained in the first and the second registers.

14. A video extractor as in claim 13 wherein the central control unit, if at least the minimum number of hits have been recorded in the range quants for which the initial azimuth values are contained in the respective registers, is enabled to generate a timing signal, and the conditional circuit comprises means to make the contents of the first and the second registers equal to each other in response to the timing signal.

15. A video extractor as in claim 13, wherein the circuit for determining the initial range of a target comprises a first and a second range register and a switch whereby, as soon as a new echo is established in a certain range quant, the conditional circuit forming part of the azimuth control circuit acts on said switch to pass the range value, supplied by the range counter, to the memory, and whereby the initial range values fetched from memory for the successive range quants and contained in the corresponding words are shifted successively through the first and the second range registers and are subsequently returned to the memory via said switch, provided that said switch is not in the position in which the instantaneous range value is passed to the memory.

16. A video extractor as in claim 15, wherein the central control unit, in case at least the minimum number of hits has been recorded in the range quants of which the initial range values are contained in the respective registers, is enabled to generate a timing signal and the conditional circuit comprises means to make the contents of the first and the second registers equal to each other in response to the timing signal.

17. A video extractor as in claim 15, wherein the circuit for determining the initial range of a target comprises a comparator for comparing the range value supplied by the range counter with a fixed value indicating the end of the range to be covered, which comparator supplies thereupon a signal indicating that the memory-stored words, corresponding with range quants exceeding said fixed value, can be erased.

18. A video extractor as in claim 1 wherein the range interval counting unit comprises a first range interval counter for counting the range quants in which hits contributing to the build-up of a target have been recorded, counting from the most distant range quant in which hits of the target have been recorded for the longest time, and a second range interval counter for counting the range quants, which contain hits contributing to the build-up of a target and which are situated before the most distant range quant in which hits of the target have been recorded for the longest time.

19. A video extractor as in claim 18, wherein the range interval counting unit comprises a range interval combination circuit which generates the range interval count by summing the counts of the first and second range interval counters and by incrementing the so obtained value by 1.

20. A video extractor as in claim 19, wherein the range interval combination circuit comprises a comparator for comparing the range interval count with a present maximum interval criterion, whereby, if said criterion has been met, a signal is applied to the readout circuit to block the readout of the word containing the respective range interval data.

21. A video extractor as in claim 19, wherein the range interval combination circuit comprises a comparator for comparing the range interval count with a preset minimum interval criterion, whereby, if said minimum interval criterion has been met, a signal is applied to the readout circuit to block the readout of the word containing the respective range interval data.

22. A video extractor as in claim 18, wherein the first range interval counter comprises a first and a second register, an upcounter and a downcounter, whereby the counts fetched from memory for the successive range quants and contained in the corresponding words are transferred to said first register, incremented by 1 in said upcounter if the data in the word of which the first range interval count is contained in the first register, is placed in the preceding word fetched from memory, of which preceding word the first range interval count is contained in the second register, which first range interval counts are transferred to the second register, incremented by 1 in said downcounter if the data in the word of which the first range interval count is contained in the second register is placed in the following word fetched from memory, of which following word the first range interval count is contained in the first register, and are shifted back into memory.

23. A video extractor as in claim 22, wherein the first range interval counter comprises a switch, controlled by the central control unit, for causing the first range interval count to be shifted back into memory if:

the word containing said first range interval count is read out;

the data in said word is to be transferred to the preceding word fetched from memory; and

the hits recorded in the relevant range quant cannot or cannot yet be regarded as belonging to the target detected in the preceding range quant.

24. A video extractor as in claim 22, wherein the first range interval counter comprises a comparator, for indicating whether the contents of the first register are greater or smaller than the contents of the second register, and an AND circuit for responding to the data provided by said comparator and to the H bits of the range quants of which the first range interval counts are contained in the respective registers, by equalizing, in case two echoes merge into one hit cluster, the first range interval count of said hit cluster and the smaller of the two first range interval counts.

25. A video extractor as in claim 18, wherein the second range interval counter comprises a first and a second register and a range interval modification circuit, whereby the range interval counts fetched from memory and contained in the corresponding words are transferred to the first register, if necessary incremented or decremented in steps in said range interval modification circuit, and shifted back into memory via said second register, and where said second range interval counter further comprises a range interval step correction circuit, in which correction circuit, in case a number of successive range quants contain information contributing to the build-up of the target and meet the miss criterion at the same time, said number of successive range quants is determined to subsequently increment the count of the second range interval counter, and in which correction circuit, if thereafter again in a number of successive range quants the first detection criterion is reached at the same time, said number of range quants is determined to decrement the count of the second range interval counter, which count cannot assume a negative value.

26. A video extractor as in claim 25, wherein the second range interval counter comprises a range interval transfer circuiit including a comparator and a logic circuit, said comparator indicating whether the contents of the first register are greater or smaller than the contents of the second register, and said logic circuit responding to the comparator-supplied data and to the H bits of the range quants of which the second range interval counts are contained in the respective registers, by equalizing, in case two echoes merge into one hit cluster, the second range interval count of the hit cluster so produced and the greater of the two second range interval counts.

27. A video extractor as in claim 1, wherein the arithmetic unit comprises a circuit for splitting a hit cluster into two separate parts in which circuit, when the magnitude of the shadow area of the hit cluster meets a splitting criterion, a signal is generated to split the hit cluster.

28. A video extractor as in claim 27, wherein the circuit for splitting a hit cluster comprises a counter for determining the magnitude of the shadow area of the hit cluster, a first comparator connected to said counter for indicating when the count of said counter has reached the present splitting criterion, in which case the range value of the range counter, decremented by the magnitude of the splitting criterion, is written into a register thereto incorporated and a second comparator for comparing the value contained in said register with the range value of the range counter, said second comparator, if in the radar sweep following that in which the value of said register is applied to the second comparator the range value equals the value in said register, supplying a signal for determining in the control bit recording means the H bit of the foremost of the parts produced by splitting.

29. A video extractor as in claim 28, wherein the control bit recording means comprises a bistable element for recording the status of the splitting bit (S bit) indicating that the H bit of the two parts produced by splitting has been determined and that the hit cluster can be split.