Programmable sequential logic array mechanism

• US 4,357,678 A
• Filed: 12/26/1979
• Issued: 11/02/1982
• Est. Priority Date: 12/26/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Davis, Gordon T.
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): MILLS, JOHN G
• Application Number:
  US06/106,824
• Time in Patent Office: 1,042 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/716, 307/465
• US Class Current: 326/39
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable
• CPC Class Codes: H03K 19/1772 with synchronous operation of at least one of the logical matrixes

Abstract

A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.

Claims

1. A programmable sequential logic array mechanism for performing logical operations and solving logical equations and comprising:

an input random access storage array having addressable plural-bit sotrage locations for storing input control words for testing for different input signals conditions;

input circuitry for receiving a plurality of binary input signals and for receiving input control words from the input storage array and producing binary truth signals indicating the states of agreement between the input signal conditions and the test conditions represented by the input control words;

a plurality of binary output bistable circuits for providing a plurality of binary output signals;

an output random access storage array having addressable plural-bit storage locations for storing output control words for controlling the states of the binary output bistable circuits;

address generating circuitry for sequentially generating a series of different storage addresses and for supplying each such address to the address circuitry of both the input and the output storage arrays, for sequentially reading out the desired control words;

and control circuitry connecting the input circuitry with binary output bistable circuits and responsive to the truth signals produced by the input circuitry for enabling the binary output bistable circuits to respond to selected output control words.

2. A programmable sequential logic array mechanism in accordance with claim 1 wherein the input circuitry includes:

circuitry for comparing each input signal with a different bit position in an input control word for producing a comparison signal indicating the relative truth value of the input signal;

and a logic circuit responsive to the various comparison signals for producing a binary truth signal indicating whether the various input signals as a group correspond to the logical conditions specified by the input control word.

3. A programmable sequential logic array mechanism in accordance with claim 1 wherein:

each storage location in the input storage array includes two bit positions for each input signal;

the input circuitry includes for each input signal a selector circuit followed by a compare circuit, with one input storage array bit position for each input signal being connected to a different one of the selector circuits and the other bit position for each input signal being connected to a different one of the compare circuits;

and the input circuitry includes a logic circuit for receiving the outputs of all of the compare circuits and producing an output truth signal of predetermined truth value when the outputs of all of the compare circuits have an identical predetermined truth value.

4. A programmable sequential logic array mechanism in accordance with claim 3 wherein each selector circuit is an AND circuit, each compare circuit is an EXCLUSIVE OR circuit and the logic circuit is an AND circuit.

5. A programmable sequential logic array mechanism in accordance with claim 1 wherein the address generating circuitry is comprised of an address counter driven by a free-running clock pulse generator.

6. A programmable sequential logic array mechanism in accordance with claim 1 wherein the input circuitry includes circuitry for providing plural-bit partitioning of the input signals.

7. A programmable sequential logic array mechanism in accordance with claim 6 wherein:

the input signals are divided into groups;

a multiplexer circuit is provided for each group of input signals;

the input signals of each group are supplied to the select inputs of its multiplexer circuit;

the input storage array supplies to the data inputs of each multiplexer a plurality of signals representing different product term combinations for the input signals in such group;

and the outputs of the various multiplexer circuits are connected to a logic circuit which produces for each input control word a binary truth signal indicating the state of agreement between the various input signal conditions and the logical combination represented by the input control word, the various successive binary truth signals produced by this logic circuit being the truth signals to which the control circuitry is responsive.

8. A programmable sequential logic array mechanism in accordance with claim 6 wherein:

each pair of input signals is connected to the select input terminals of a different four-to-one multiplexer circuit;

the four data terminal inputs of each such multiplexer circuit is connected to a different group of four control word output lines of the input storage array;

and the data output terminals of the different multiplexer circuits are coupled to a logic circuit for producing the binary truth signals to which the control circuitry is responsive.

9. A programmable sequential logic array mechanism in accordance with claim 1 and including:

circuitry for time multiplexing input signals into the input circuitry;

and circuitry for synchronizing the addressing of the input and output storage arrays with the input signal multiplexing for providing different input and output control words for each set of the time multiplexed input signals.

10. A programmable sequential logic array mechanism in accordance with claim 9 wherein:

the input circuitry includes a plurality of input signal lines;

the sequential logic array mechanism includes a separate multiplexer circuit for each input signal line for time multiplexing N different input signals onto each such input signal line;

the control words in the input and output storage arrays are organized in groups of N successive control words, different control words in each group corresponding to the different ones of the N sets of signals which are time multiplexed onto the input signal lines;

and the control circuitry includes circuitry for detecting for each repetition of the multiplexing of the N sets of input signals the occurrence of N successive truth signals of the same predetermined truth value for enabling N groups of output stages to respond to different ones of the control words in the corresponding group of N output control words.

11. A programmable sequential logic array mechanism in accordance with claim 10 wherein the control circuitry includes circuitry responsive to the occurrence of a truth signal having a value opposite to the predetermined value for resetting the multiplexing sequence and for advancing the address generating circuitry to the starting address for the next group of N control words.