Double redundant processor

• US 4,358,823 A
• Filed: 04/12/1979
• Issued: 11/09/1982
• Est. Priority Date: 03/25/1977
• Status: Expired due to Term

• Current Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: McDonald, John C., Baichtal, James R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/029,380
• Time in Patent Office: 1,307 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/9, 371/68
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1645 and the comparison itself uses redundant hardware
• CPC Class Codes: G06F 11/165 with continued operation after detection of the error
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/2033 switching over of hardware resources
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups

Abstract

A double redundant processor including first and second master processors for processing data, control and address signals in a data processing system. The first master processor is in an active state for processing the signals and the second master processor is in a standby state for processing the signals. The first and second master processors include first and second subprocessors for simultaneously processing the data, control and address signals, a comparator connected to compare the signals from the first and second subprocessors, thereby generating a comparison error signal if a disagreement exists, and an alarm monitor responsive to the error signal for inactivating the active master processor and activating the standby master processor.

Claims

1. In a data processing system, a double redundant processor comprising:

first and second master processors for processing data, control and address signals of said system where said first master processor is in an active state for processing said signals and said second master processor is in a stand-by state for processing said signals, said first and second master processors each including;

first and second subprocessors having a common memory for simultaneously processing said signals, said first subprocessor having means for transmitting to and receiving from said system said data, control and address signals of said system and said second subprocessor having means for receiving said data, control and address signals of said system,

comparator means connected to continuously compare all of the processed signals from said first and second subprocessors for generating a comparison error signal when a comparison error occurs in the active master processor, and

alarm monitor means responsive to said error signal for inactivating the active master processor and activating the stand-by master processor when said error signal occurs.

2. A processor as in claim 1 further including a bidirectional common data bus for carrying said data signals into and out from said master processor, a first bidirectional driver/receiver for connecting said data signals between said common bus and said first subprocessor, and for connecting said data signals between said first subprocessor and said comparator means.

3. A processor as in claim 2 further including a second bidirectional driver/receiver for connecting said data signals between said common bus and said second subprocessor, a first unidirectional data bus for connecting said second driver/receiver to said second subprocessor, and a third unidirectional data bus connected between said second data bus and said comparator means for connecting said data signals from said second subprocessor to said comparator means.

4. A processor as in claim 1 wherein said comparator means include data comparator means for comparing said data signals, control comparator means for comparing said control signals, and address comparator means for comparing said address signals.

5. A processor as in claim 1 further including a first common control bus for connecting input control signals to said first and second subprocessors, a second common output control bus, a first output control bus for connecting output control signals from said first subprocessor to said second common bus and to said comparator means, a second output bus for connecting said second subprocessor to said comparator means.

6. A processor as in claim 1 further including a first output address bus connected to said first subprocessor for outputting address signals, a second address bus connected between said first address bus and said comparator means, and a third address bus connected between said second subprocessor and said comparator means.

7. A processor as in claim 4 further including logic means responsive to said comparator output means for connecting said error signal to said alarm monitor means.

8. A processor as in claim 7 wherein said logic means include enabling means connected to said comparator means, said enabling means responsive to predetermined control signals from said second subprocessor thereby enabling said error signal.

9. A processor as in claim 2 where said data signals include a first parity signal and wherein said first driver/receiver includes parity generator means for generating a second parity signal corresponding to the parity of said data signal, logic means connected to receive said first and second said parity signals, thereby generating a parity error signal when said signals differ.

10. A processor as in claim 1 wherein said alarm monitor means include

a first alarm monitor connected to receive an error signal from said first master processor whereby said first monitor generates an alarm signal,

a second alarm monitor connected to said second master processor and to said first alarm monitor for receiving said alarm signal whereby said second master processor is activated and said first master processor is inactivated.

11. A processor as in claim 1 wherein said alarm monitor means include logic means connected to receive said error signal for providing said alarm signal to said other master processor.

12. A processor as in claim 11 wherein said logic means include driver means responsive to said alarm signal connected to inactivate said first master processor.

13. A double redundant processor for controlling the operation of an integrated message accounting system, said processor comprising:

master clock means responsive to an active signal for activating said system,

first and second master processors for processing data, control and address signals of said accounting system where said first master processor is in an active state for processing said signals and said second master processor is in a stand-by state for processing said signals, said first and second master processors each including;

first and second subprocessors having a common memory for simultaneously processing said signals, said first subprocessor having means for transmitting to and receiving from said system said data, control and address signals of said system and said second subprocessor having means for receiving said data, control and address signals of said system,

comparator means connected to continuously compare all of the processed signals from said first and second subprocessors for generating a comparison error signal when a comparison error occurs in the active master processor,

means for generating said active signal, and

alarm monitor means responsive to said error signal for inactivating the active master processor and activating the stand-by master processor when said error signal occurs.

14. In an integrated message accounting system, a double redundant processor for controlling the operation of the system comprising:

first and second master processors for processing data, control and address signals of said accounting system where said first master processor is in an on-line state for actively processing said signals and said second master processor is in an off-line stand-by state for processing said signals, said first and second master processors each including;

first and second subprocessors having a common memory for simultaneously processing said signals, said first subprocessor having means for transmitting and receiving said data, control and address signals of said system and said second subprocessor having means for receiving said data, control and address signals of said system and

comparator means connected to continuously compare said processed signals from said first and second subprocessors for generating a comparison error signal when a comparison error occurs in the active master processor,

first and second master clocks responsive to an active signal for activating said system,

a first alarm monitor including means for generating a first active signal thereby activating said first master clock and means for generating a first on-line signal when said first master processor is active and on-line, said first alarm monitor including means responsive to a first error signal from said first master processor for generating a first alarm signal and means responsive to said first alarm signal for changing said first on-line signal to a first off-line signal,

a second alarm monitor including means for generating a second active signal thereby activating said second master clock and means for generating a second on-line signal, said second alarm monitor including means responsive to a second error signal from said second master processor for generating a second alarm signal, said second alarm monitor connected to receive said first on-line signal and responsive thereto for preventing said second master processor from actively processing said signals, said second alarm monitor including means responsive to said first on-line signal for generating said second active signal when said first on-line signal changes to said off-line signal, thereby activating said second master clock and said second master processor,

said first alarm monitor connected to receive said second on-line signal and responsive thereto for preventing said first master processor from actively processing said signals.

15. In a digital telephone system having a double redundant processor including first and second master processors for processing information signals where said first master processor is in an active state for processing said signals and the second master processor is in a stand-by state for processing said signals, said first and second master processors each including first and second subprocessors having a common memory for simultaneously processing said signals, said first subprocessors having means for transmitting to and receiving from said system said information signals of said system and said second subprocessors having means for receiving said information signals of said system, the method of checking the operation of said master processors comprising the steps of:

continuously comparing all of the processed signals of said first and second subprocessors,

generating a comparison error signal when a comparison error occurs in the active master processor, and

inactivating the first master processor and activating the second master processor in response to an occurrence of said error signal from the first master processor.

16. In a digital telephone system, a double redundant processor comprising:

first and second master processors for simultaneously processing information signals of said system where said first master processor is in an active state for processing said signals and said second master processor is in a stand-by state for processing said signals, said first and second master processors each including;

first and second subprocessors having a common memory for simultaneously processing said signals, said first subprocessors having means for transmitting to and receiving from said system said data, control and address signals of said system and said second subprocessor having means for receiving said data, control and address signals of said system,

comparator means connected to continuously compare all of the processed signals from said first and second subprocessors for generating a comparison error signal when a comparison error occurs in the first active master processor, and

alarm monitor means responsive to said error signal for inactivating the first master processor and activating the second master processor when said error signal occurs.