Control circuitry for data transfer in an advanced data link controller

• US 4,358,825 A
• Filed: 03/21/1980
• Issued: 11/09/1982
• Est. Priority Date: 06/30/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hepworth, Edward C., Kyu, Shikun
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/132,438
• Time in Patent Office: 963 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/83, 370/89
• US Class Current: 710/106
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/5692 Selection among different networks

Abstract

A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Claims

1. In a data link controller for controlling data communications between a bidirectional data bus and a communications link transmitting and receiving data in serial form, said data link controller comprising a transmitter and a receiver, the improvement wherein said receiver comprises:

control means for controlling a multi-byte FIFO register comprising a plurality of N-bit registers, N being a positive integer, a first one of said N-bit registers being responsive to data received from said communications link, and each succeeding N-bit register being responsive bit-for-bit to the contents of the immediately preceding N-bit register, said bidirectional data bus being responsive to the contents of the last of said N-bit registers;

means for generating a clock signal for enabling data to transfer byte by byte on each transition of the clock signal that transfers data to the bidirectional data bus from the communications link; and

means responsive to said clock signal for transferring data through said plurality of N-bit registers on each transition of said clock signal, and

wherein said transmitter comprises;

control means for controlling a multi-byte FIFO register comprising a plurality of N-bit registers, N being a positive integer, a first one of said N-bit registers being responsive to said bidirectional data bus, and each succeeding N-bit register being responsive bit-for-bit to the contents of the immediately preceding N-bit register, said communications link being responsive to the contents of the last of said N-bit registers;

means for generating a clock signal for enabling data to transfer byte by byte on each transition of the clock signal from the bidirectional data bus to the communications link; and

means responsive to said clock signal for transferring data through said plurality of N-bit registers on each transition of said clock signal.

2. The data link controller recited in claim 1 further comprising:

identifying means having a plurality of temporary storage means, each of said temporary storage means being associated with a respective one of said N-bit registers and storing an indication indicating whether the contents of the N-bit register is full or empty.