Digital erase of raster lines

• US 4,360,805 A
• Filed: 10/01/1980
• Issued: 11/23/1982
• Est. Priority Date: 10/01/1980
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Williams, Eugene C., Andrews, Edward W.
• Primary Examiner(s): Trafton, David L.
• Application Number:
  US06/192,736
• Time in Patent Office: 783 Days
• Field of Search: 340/744, 340/726, 340/724, 340/728, 340/791, 340/811, 358/111, 358/244, 358/242, 315/371, 315/31 TV
• US Class Current: 345/20
• CPC Class Codes: H04N 3/30 otherwise than with constant velocity or otherwise than in pattern formed by unidirectional, straight, substantially horizontal or vertical lines
• CPC Class Codes: H04N 5/843 on film

Abstract

The perception of raster lines on a television monitor is obscured by continuously and cyclically vertically shifting and presenting in successive frames the raster in successive upward positions and then in successive downward positions by incremental amounts, the total maximum vertical shift distance being less than the distance between original horizontal raster lines, thus giving the appearance of blending the information between original horizontal raster lines. Vertical raster deflection is accomplished by cyclically delaying the original, or normal, vertically sync pulses by amounts which incrementally increase to a maximum for producing a vertical frame rise less than the distance between original horizontal raster lines and decrementally decrease to no delay. A photographic camera capable of multiple frame exposure time is used to produce photographs of the video monitor without connections or operational dependence upon the television monitor system. An all-digital system provides increased reliability and repeatability as well as manufacturing and maintenance economies.

Claims

1. A method of obscuring the perception of a base raster of a raster scan display device by bidirectionally vertically shifting said base raster in a manner in which a sequence of other rasters are produced with a maximum shift of any one of such other rasters in either direction being less than the distance between a pair of adjacent horizontal scan lines of said base raster, said base raster being produced by scanning an electron beam in response to original vertical and horizontal sync pulses, said method comprising:

presenting a predetermined number of rasters with the horizontal lines thereof shifted vertically by a predeterminedly-changed amount in a cyclical sequence wherein

(a) in one stage of said sequence, rasters are presented each at an increasingly higher position relative to the position corresponding to said base raster in response to

(i) delayed vertical sync signals each of which is predeterminedly increasingly delayed relative to the corresponding original vertical sync pulses, and to

(ii) original horizontal sync pulses, and

(b) in an opposite stage of said sequence, rasters are presented each at a lower position relative to the immediately preceding raster in response to

(i) delayed vertical sync signals each of which is delayed by a predeterminedly decreased amount of time relative to the time of delay of the immediately preceding delayed vertical sync signal, and to

(ii) original horizontal sync pulses.

2. A method of obscuring the perception of a base raster of a raster scan display device by bidirectionally vertically shifting said base raster in a manner in which a sequence of successive rasters are produced with the maximum shift of any successive raster in either direction being less than the distance between a pair of adjacent horizontal scan lines of said base raster, said method comprising the steps of:

(a) presenting a base raster produced by scanning an electron beam in response to

(i) original vertical sync pulses and to

(ii) original horizontal sync pulses, and

(b) then presenting a predetermined number of successive rasters with the horizontal lines thereof shifted vertically by a predeterminedly-changed amount in a cyclical sequence, wherein

(A) in one stage of said sequence, rasters are presented each at an increasingly higher position relative to the position corresponding to said base raster in response to

(i) delayed vertical sync signals each of which is predeterminedly increasingly delayed relative to the corresponding vertical sync pulses, and to

(ii) original horizontal sync pulses, and

(B) in a subsequent stage of said sequence, the balance of said successive rasters are presented each at a lower position relative to the immediately preceding one of said successive rasters in response to

(i) delayed vertical sync signals each of which is predeterminedly delayed by a decreased amount of time relative to the time of the delay of the immediately preceding delayed vertical sync signal, and to

(ii) original horizontal sync pulses.

3. In apparatus for use with raster scan display device having input means for receiving vertical sync signals for initiating vertical deflection, horizontal sync signals for initiating horizontal deflection, and separate picture information signals, and a display tube controllable by successive vertical sync signals to produce successive rasters comprised of vertically-spaced horizontal lines intensity modulated by said picture information signals, the improvement which results in the presentation of:

(i) a base raster produced in response to original vertical sync signals corresponding to original vertical sync pulses and original horizontal sync signals identical to original horizontal sync pulses, and

(ii) a predetermined number of shifted rasters displayed with the horizontal lines thereof shifted vertically in sequence, and wherein in said sequence a predetermined number of said shifted rasters are shifted vertically upward, each by a predetermined amount relative to the position of said base raster, with the horizontal lines of the highest-shifted raster being below the next upwardly-adjacent horizontal lines of said base raster, to thereby reduce perception of space between the horizontal lines in the base raster, said improvement comprising;

(a) means effective in response to the occurrence of a sequence of a predetermined number of said original vertical sync pulses for producing a vertical sync signal for each of said original vertical sync pulses, with the produced vertical sync signals occurring in a multistage cycle wherein;

(i) in one stage a predetermined number of produced vertical sync signals are each delayed by a predeterminedly increased amount of time relative to the original vertical sync signal with which each corresponds but short of being delayed such that the horizontal lines of the highest-shifted raster lines would correspond with the immediately upward-adjacent horizontal lines of the base raster,

(ii) in another stage, a predetermined number of produced vertical sync signals are each delayed by a predeterminedly decreased amount of time relative to the time of delay of the immediately preceding produced vertical sync signal; and

(b) means for controlling said display device in response to;

(i) the horizontal sync signals for said raster, and to

(ii) said produced vertical sync signals.

11. An apparatus as set forth in claim 3 wherein said produced vertical sync signals include, in still another stage, an undelayed produced vertical sync signal.

4. Means for vertically shifting a predetermined number of rasters representing a picture on the display tube of a raster scan display device in order to obscure the presentation of the horizontal lines of said rasters ordinarily visible on the face of the display device, said means comprising:

(a) means for producing uniformly-timed trains of original horizontal sync pulses and original vertical sync pulses;

(b) means responsive to the occurrence of a sequence of original vertical sync pulses for cyclically producing a sequence of delayed vertical sync signals corresponding respectively to the shifted rasters to be presented and to the original vertical sync pulses wherein;

(A) in one stage of said sequence a predetermined number of produced vertical sync signals are each delayed by a predeterminedly increased amount of time relative to the timing of a respective original vertical sync pulse, and

(B) in another stage of said sequence, a predetermined number of produced vertical sync signals are each delayed by a predeterminedly decreased amount of time relative to the delay time of the immediately preceding produced vertical sync signal.

12. A shifting means as set forth in claim 4 wherein said occurrence responsive means also produces an undelayed vertical sync signal and wherein there is included means for supplying said delayed vertical sync signals for each raster to said monitor as an alternative to supplying the corresponding o

5. In apparatus for use with a system having a raster scan display device operative under the control of video information signals and horizontal and vertical sync signals;

the improvement constituting means for vertically shifting the raster of said display device thereby to obscure the perception of the lines of said raster, said improvement comprising;

(a) means for producing a sequence of original horizontal sync pulses and original vertical sync pulses;

(b) means for producing an End-of-Field pulse a predeterminedly-fixed amount of time after each original vertical sync pulse;

(c) means for producing a Change-Count pulse (i) identical to said End-of-Field pulse when said display device is operated in a non-interlace mode and (ii) in response to every other End-of-Field pulse when said device is operated in an interlace mode;

(d) horizontal sync signal input means connected to said display device;

(e) vertical sync signal input means connected to said display device;

(f) means for supplying said sequence of horizontal sync pulses to said horizontal sync signal input means;

(g) bidirectional counter means having a binary memory, input means for receiving said Change-Count pulses as clock pulses to said bidirectional counter means, output means representing the binary state of said binary memory, and said bidirectional counter means being effective for cyclically counting up and counting down the binary state of said memory in response to said Change-Count pulses received at said input means;

(h) means controlled by said output means of said bidirectional counter means for producing a sequence of vertical sync signals each of which is delayed relative to a respective original vertical sync pulse by an amount of time proportionally related to said binary state of said binary memory of said bidirectional counter; and

(i) means for supplying said sequence of produced vertical sync signals to said vertical sync signal input means to said display device.

6. In apparatus for use with a raster scan display device operative under the control of video information signals, horizontal sync signals, and vertical sync signals, the improvement constituting means for vertically shifting said raster thereby to obscure the perception of the lines thereof, said improvement comprising:

(a) means for producing a sequence of original horizontal sync pulses and original vertical sync pulses;

(b) means for producing an End-of-Field pulse a predeterminedly-fixed amount of time after each original vertical sync pulse;

(c) interlace flip-flop means for producing Change-Count pulses in response to;

(i) End-of-Field pulses when said display device is operated in a non-interlace mode; and

(ii) alternate End-of-Field pulses when said display device is operated in an interlace mode;

(d) horizontal sync signal input means connected to said device;

(e) vertical sync signal input means connected to said device;

(f) means for supplying said sequence of original horizontal sync pulses to said horizontal sync signal input means;

(g) bidirectional counter means having a binary memory storing a binary state, input means for receiving said Change-Count pulses as clock pulses to said bidirectional counter means, output means outputting the binary state of said binary memory and having output bits corresponding in number to the bits of said binary memory, and said bidirectional counter means being effective for cyclically counting up and counting down the binary state of said memory in response to said Change-Count pulses received at said input means;

(h) shift register means comprising a shift register input, and a contents having bit positions corresponding in number to at least the number of frames to be displayed as interlineations between two of the original horizontal raster lines;

(i) programmable clock generator means having a clock system output for providing output clock pulses to said input of said shift register, with a period of each of said output clock pulses being selectively predetermined and such that the time equal to the product of

(1) the number of interlineations multiplied by

(2) the period of said programmable clock generator output clock pulse is less than the time between original vertical sync pulses;

(j) data select means for selecting the bit position of said contents of said shift register means corresponding to the binary state of said binary memory of said bidirectional counter;

(k) output means for supplying to said vertical sync signal input means the signal on the bit position of said contents of said shift register means selected by said data select means as the delayed vertical sync signal and in the same sequence as generated, whereby

(i) the original vertical sync pulse is received by said shift register means,

(ii) said original vertical sync pulses are right-shifted through the bit positions of said shift register means one position for each said output clock pulse of said programmable clock generator,

(iii) a train of binary information in said bit position of said shift register means corresponding to the binary state of said binary memory of said bidirectional counter is fed by said data select means to said output means,

(iv) each bit of said train of binary information in said bit position of said shift register means reaches said output means delayed relative to its corresponding original vertical sync pulse by an amount of time equal to said binary state of said binary memory of said bidirectional counter multiplied by the period of a single output clock pulse,

(v) an End-of-Field pulse is produced,

(vi) a Change-Count pulse

(a) identical to said End-of-Field pulse when said display device is operated in a non-interlace mode, and

(b) responsive to every other End-of-Field pulse when said display device is operated in an interlace mode is received by said bidirectional counter, and

(vii) said binary state of said binary memory of said bidirectional counter is changed by one in one direction when said binary state of said binary memory of said bidirectional counter had most previously been all zero bits rather than all one bits and is changed by one in the opposite direction when said binary state of said binary memory had most previously been all one bits rather than all zero bits.

7. The invention of claim 6, wherein said programmable clock generator means comprises:

(a) a basic clock input means providing basic clock input pulses;

(b) an n-bit position switch having 2ⁿ binary settings and an n-bit position output;

(c) an n-bit binary counter having a count, a clock input connected to said basic clock input means, a reset input, a load input, a ripple-carry output, and an n-bit input setting connected to the n-bit position output of said n-bit position switch;

(d) a flip-flop having an output, an input connected to said ripple-carry output of said binary counter, and a clock input connected to said basic clock input means wherein said output of said flip-flop changes state when concurrently said input of said flip-flop is at a logic "1" logic state and a clock pulse occurs at said clock input;

(e) load means to provide a logic "1" to said load input of said binary counter when both said input of said flip-flop and said output of said flip-flop are both logic "1" whereby said count of said binary counter is set to said binary setting of said n-bit position switch upon the occurrence of the next basic clock input pulse at said clock input of said binary counter; and

(f) said clock system output has said output of said flip-flop connected thereto whereby said clock system output provides a logic "1" output for 2ⁿ periods of the basic clock input pulse followed by a logic "0" output for a multiple of periods of the basic clock input pulse equal to (2ⁿ minus said manual setting of said n-bit position switch).

8. The invention of claim 6, wherein said bidirectional counter means comprises:

(a) a bidirectional up/down counter having a binary memory including a binary state, a clock input, an up/down input bit, a load input, and a ripple-carry output wherein said clock input is connected to said interlace flip-flop means for receiving said Change-Count pulses, said ripple-carry output is energized when the binary state of said binary memory is either all zeros or all ones, said up/down input bit is either a logic "0" or a logic "1" and determines whether said bidirectional up/down counter will count up or count down;

(b) a direction flip-flop having an output, a clock input, and a direction-state memory wherein said direction-state memory is either a logic "0" or logic "1," said output of said direction flip-flop being the same logic state as said direction-state memory, said direction-state changes to the opposite binary logic state upon the concurrence of (i) a Change-Count pulse and (ii) an energization of said ripple-carry output of said bidirectional up/down counter at said clock input of said direction flip-flop;

whereby said binary memory of said bidirectional counter means provides a binary counting sequence which alternately counts up and counts down in response to said Change-Count pulses.

9. The invention of claim 6, wherein said data select means comprises:

(a) first and second stages of data selector units each having (1) a plurality of data input bits, (2) a plurality of select bits connected to all but the highest bit of said output bits of said bidirectional counter means, (3) a strobe input, and (4) a stage output, wherein

(i) the number of data input bits of all data selector units total at least the number of bit positions of said contents of said shift register means,

(ii) each of said data input bits is connected to a corresponding bit position of said contents of said shift register means,

(iii) said first stage data selector unit of said data selector means is connected to the highest bit of said output bits of said bidirectional counter means,

(iv) said select bits are decoded to select the bit corresponding to the decimal number equivalent to the binary state of said select bits of said data input bits of said data selector unit when said strobe input of said data selector unit is energized whereupon the logic state at said corresponding bit of said corresponding data input bit is transferred to said stage output of said data selector unit,

(b) an inverter having an input and an output, said output being at the opposite binary logic state to that at said input, said input of said inverter is connected to the highest bit of said output bits of said bidirectional counter means and said output of said inverter is connected to said strobe bit of said second stage data selector unit;

(c) a data select output connected to said stage outputs of both stages of said data selector units and having the same logic state as that of the stage output of the data select unit stage which has its strobe input enabled.

10. The invention of claim 6, wherein said shift register means comprises first and second stages of shift register units each having (1) a clock input, (2) a shift register unit input, and (3) a plurality of bit storage positions, the total of bit storage positions of all said stages of shift register units being said contents of said shift register means, and wherein

said first stage handles the lower bits of said shift register means,

said second stage handles the upper bits of said shift register means,

the first position of said bit storage positions of each stage being that which would receive the logic state at said shift register unit input of said stage upon the occurrence of the next clock pulse at said clock input of said stage,

the last position of said bit storage positions of each stage being that storage position which would receive the logic stage introduced at the shift register unit input of said stage which is most delayed in time among all bit storage positions of said stage, whereby each bit storage position will have transferred to it the binary logic state of the previous bit storage position upon occurrence of each clock pulse at said clock input of said stage,

said input of said shift register means is connected to said shift register unit input of said first stage shift register unit, said last bit storage position of said first stage shift register unit is connected to the shift register unit input of said second stage shift register unit,

said clock system output of said programmable clock generator is connected to the clock inputs of both said stages of shift register units for providing output clock pulses to said clock inputs of both said stages, and

said means for producing a sequence of original vertical sync pulses is connected to said shift register unit input of said first stage shift register unit.