Arrangement for detecting defects during the asynchronous transfer of digital measured values

• US 4,360,918 A
• Filed: 08/18/1980
• Issued: 11/23/1982
• Est. Priority Date: 09/08/1979
• Status: Expired due to Term

• Current Assignee: Wabco Westinghouse Fahrzeugbremsen GmbH
• Original Assignee: Wabco Westinghouse Fahrzeugbremsen GmbH
• Inventors: Pape, Klaus, Auding, Rudolf, Ruhnau, Garhard
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US06/179,355
• Time in Patent Office: 827 Days
• Field of Search: 371/69, 371/70, 371/32, 371/33, 303/92, 364/426
• US Class Current: 714/37
• CPC Class Codes: B60T 8/885 using electrical circuitry
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 11/1497 Details of time redundant execution on a single processing unit
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence

Abstract

An arrangement for detecting defects during the asynchronous transfer of digital measured values in a microcomputer system including an input circuit for producing the digital measured values. A storage register temporarily stores the digital measured values received from the input circuit. A multiplexer transmits the stored digital measured values to a microcomputer for further processing. The stored digital measured values are consecutively transmitted twice so that the microcomputer performs a comparison of both of the digital measured values. If both of the digital measured values are the same, the microcomputer processes the digital measured values. If the digital measured values are different, the multiplexer repeats the double transmission of the digital measured values.

Claims

1. An arrangement for recognizing errors during the asynchronous transmission of digital measured values into a microcomputer comprising, an input circuit for producing the digital measured values, a plurality of data lines coupled between said input circuit and an intermediate storage circuit for feeding the digital measured values in parallel into said intermediate storage circuit in response to a pulse on a control line, a plurality of output lines coupled between said intermediate storage circuit and a multiplexer for feeding the digital measured values in parallel into said multiplexer, a common data line coupled between said multiplexer and a microcomputer for providing a first dual transmission of two successive digital measured values serially into said microcomputer in response to signals on a plurality of address lines leading from said microcomputer to said multiplexer, and said microcomputer compares the first measured values with the second measured values of said first dual transmission to determine equality for causing further processing by said microcomputer when equality exists and for causing a second dual transmission of the digital measured values when an inequality exists and also when the digital measured values lie outside the limits of an upper and lower boundary values and produces an error signal to prevent further processing when an inequality exists in both dual transmissions and also when the digital measured values of both transmissions lie outside of the upper and lower boundary values.