Microcomputer with logic for selectively disabling serial communications

• US 4,361,876 A
• Filed: 09/05/1978
• Issued: 11/30/1982
• Est. Priority Date: 09/05/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Groves, Stanley E.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US05/939,742
• Time in Patent Office: 1,547 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 179/15 AL, 340/147 LP
• US Class Current: 710/32
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.

Claims

1. In a single chip microcomputer having a processor and a data bus coupled thereto, a serial communication control circuit for selectively coupling serial information received on a serial I/O line to the processor via the data bus, the control circuit comprising:

storage means coupled to said processor via said data bus, for storing a first predetermined binary logic state in response to receiving a first control signal for enabling said serial communication circuit provided by said processor via said data bus, and a second predetermined binary logic state in response to receiving a second control signal for disabling said serial communication circuit,

receiver means coupled between said data bus and said serial I/O line, for receiving serial information on said serial I/O line, and for coupling said received serial information to said data bus only when said storage means is storing said first predetermined binary logic state, and

control means coupled to said receiver means and to said storage means, for applying said second control signal to said storage means in response to said receiver means receiving predetermined serial information on said serial I/O line, whereby said processor may selectively ignore serial information on said serial I/O line by storing said first logic state in said storage means to decouple the serial information from said data bus thereby relieving said processor of the burden of recovering all of every message impressed on said serial I/O one.

2. The microcomputer of claim 1 wherein the processor provides said first control signal via said data bus in response to determining from an address portion of the serial information coupled to the data bus by said receiver means that such address portion does not match a unique address assigned to said processor.

3. The microprocessor of claim 1 or 2 wherein said receiver means serially receives said serial information via said serial I/O line and couples said received information in parallel to said data bus.