Printed circuit board

• US 4,362,899 A
• Filed: 10/02/1980
• Issued: 12/07/1982
• Est. Priority Date: 10/05/1979
• Status: Expired due to Term

• Current Assignee: University College London (University of London)
• Original Assignee: University College London (University of London)
• Inventors: Borrill, Paul L.
• Primary Examiner(s): Kucia, R. R.
• Application Number:
  US06/193,109
• Time in Patent Office: 796 Days
• Field of Search: 174/32, 174/33, 174/34, 174/36, 174/117 PC, 174/117 FF, 174/68.5, 361/409, 361/410
• US Class Current: 174/36
• CPC Class Codes: H05K 1/0219 Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 2201/044 Details of backplane or midplane for mounting orthogonal PCBs
• CPC Class Codes: H05K 2201/09236 Parallel layout
• CPC Class Codes: H05K 9/0039 Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing printed shielding conductors, ground planes or power planes for reduction of cross-talk or noise in printed circuits H05K1/0218

Abstract

A three layer printed circuit board comprises upper and lower layers which provide terminal locations for connection to pins of electrical connectors or electronic components which are to be connected in parallel by conductor tracks of the circuit board. In order to achieve an even distribution of conductor tracks between the layers, only certain terminal locations are connected to respective conductor tracks, the locations of the respective layers being electrically connected by plated-through holes. A conductive layer providing a ground plane is located between the upper and lower layers and has non-conductive areas providing clearance for the plated-through holes. Shield tracks are located between the conductor tracks and are connected to the ground plane by plated-through holes so that they form closed conductive loops providing shielding against capacitative and inductive cross-talk between the conductor tracks.

Claims

1. A multilayer printed circuit board comprising:

at least two layers each having an array of linear parallel conductor tracks;

at least one layer having a conductor area forming a ground plane, said ground plane layer being disposed between said two conductor track layers;

a plurality of terminal arrays extending generally transversely to the longitudinal axes of said conductor tracks, said terminal arrays being spaced apart in the direction of the linear axes of said conductor tracks;

electrically conductive means extending through the multiple layers of the printed circuit board for each terminal of each array, whereby each individual terminal of each array is electrically connected to a corresponding individual terminal of all other arrays, and all the terminals of each array are individually electrically connected to corresponding ones of the linear conductor tracks;

each conductor track layer further having a plurality of arrays of linear parallel conductive shielding tracks, each shielding track being arranged between two adjacent conductor tracks and between two adjacent arrays of said terminals such that the opposite ends of each shielding track terminate adjacent terminal areas of said conductor tracks associated with respective ones of two adjacent terminal arrays; and

electrically conductive means for connecting each of the shielding tracks of said two adjacent conductor track layers in common to the intermediate ground plane, said electrically conductive means extending between the respective layers of the circuit board in the regions of the two opposite ends of the shielding tracks.

2. A printed circuit board according to claim 1, comprising three layers of which the two outer layers comprise said conductor track layers and the intermediate layer comprises said ground plane layer, said linear conductors of said outer layers comprising microstrip transmission lines sharing a local dielectric between air and the printed circuit board substrate.

3. A printed circuit board according to claim 1 or 2, wherein the shielding tracks of the respective outer layers are arranged in registering superimposition and each pair of superimposed shielding tracks are connected in common to the ground plane by a single pair of electrically conductive means extending through the three layers of the circuit board.