Signal transducer

• US 4,363,040 A
• Filed: 06/17/1980
• Issued: 12/07/1982
• Est. Priority Date: 06/21/1979
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Inose, Shuichi
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US06/160,162
• Time in Patent Office: 903 Days
• Field of Search: 360/40, 360/43, 360/51, 360/46
• US Class Current: 360/51
• CPC Class Codes: G11B 20/1419 to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
• CPC Class Codes: G11B 20/1423 Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code

Abstract

There is disclosed a signal transducer for extracting only the data components from information which has been modulated by different modulation systems. More concretely, the transducer provides two kinds of clock signals with respect to the information obtained by modulating the data under the frequency-modulation system or the modified frequency-modulation system, and extracts the data components from the information in accordance with one of the two kinds of clock signals.

Claims

1. A signal transducer, comprising:

(a) a phase synchronizing circuit which receives as an input thereinto information obtained by modulation of data, and produces as an output therefrom said input information and clock signals synchronized with a cycle proper to said input information;

(b) a flip-flip circuit which receives as an input thereinto the clock signal output from said phase synchronizing circuit;

(c) a first AND circuit which receives at one of the inputs thereof an output from said flip-flop circuit;

(d) a second AND circuit which receives at one of the inputs thereof the clock signals output from said phase synchronizing circuit;

(e) signal input means which receives thereinto input signals to open the other input of said first AND circuit and to open any one of the other inputs of said second AND circuit;

(f) an OR circuit which receives as input thereinto the outputs from said first and second AND circuits; and

(g) extracting means which receives as input thereinto the information output from said phase synchronizing circuit and the output from said OR circuit, and which extracts said data from said information.

2. The signal transducer as set forth in claim 1, wherein said phase synchronizing circuit receives as an input thereinto information which has been recorded in a recording medium and has been obtained from data modulated under the frequency-modulation system or the modified frequency-moduation system.

3. The signal transducer as set forth in claim 2, wherein said signal input means receives thereinto an input signal to open said first AND circuit when said phase synchronizing circuit receives as an input thereinto information obtained from data modulation under the frequency-modulation system, and receives thereinto an input signal to open said second AND circuit when said phase synchronizing circuit receives as an input thereinto information obtained from data modulated under the modified frequency-modulation system.

4. A signal transducer comprising:

phase synchronizing circuit for receiving an input information obtained from modulating data and for separately producing as an output therefrom the input information, said circuit having a clock signal synchronized with a cycle appropriate for the input information;

frequency-dividing means for receiving as an input the clock signal from said phase synchrnoized circuit and for frequency-dividing the clock signal;

6. A signal transducer as set forth in claim 4, wherein said frequency dividing means is adapted to frequency divide the clock signal input thereinto by two and said signal input means is adapted to receive thereinto input signals indicative of the frequency-modulation system and the modified frequency-modulation system for modulating data to obtain information.

8. A signal transducer as set forth in claim 4, 5 or 6, wherein said selecting means comprises a first AND circuit for receiving thereinto an input signal from said frequency-dividing means and a second AND circuit not receiving thereinto an input signal from said frequency-dividing means.

5. signal input means for receiving an input signal indicative of the system by which data is modulated to obtain information;

selecting means for selecting an output clock signal from between the clock signal produced from said phase synchronizing circuit and the clock signal which has been frequency-divided by said frequency dividing means, the selection being in accordance with the input signal received by said signal input means; and

extracting means for extracting the data components from the input information by the use of the information produced from said phase synchronizing circuit and the output clock signal selected by said selecting means.

7. A signal transducer as set forth in claim 5, wherein said selecting means is adapted to select, as the output clock signal, the clock signal which has been frequency divided by said frequency-dividing means when the input information is obtained by modulating data under the frequency-modulation system and to select, as the output clock signal, the clock signal having phase synchronized with the phase of the information when the input information is obtained by modulating data under the modified frequency-modulation system.