Communications processor

• US 4,363,094 A
• Filed: 06/04/1980
• Issued: 12/07/1982
• Est. Priority Date: 12/29/1977
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (AT&T, Inc.)
• Original Assignee: M/A-COM DCC, Inc. (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Kaul, Pradeep, Wendling, Daniel, Muzamder, Deepak, Newport, Christopher, Ford, Harold
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US06/156,451
• Time in Patent Office: 916 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/113
• CPC Class Codes: G06F 13/37 using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
• CPC Class Codes: G06F 13/4217 with synchronous protocol

Abstract

A flexible, modular communications processor is disclosed comprised of a plurality of microprocessors. A demand assigned bus is provided to couple the microprocessors through an arbitrator to an information storage and retrieval device. Each of the microprocessors comprises a conventional integrated circuit microprocessor, associated local memory, transmitters and receivers for coupling information to and from the bus and bus access circuitry, cooperating with the arbitrator to allocate the bus resource. Communication input/output is handled by a plurality of microprocessors configured as line processors, each coupled to its associated interface switch, which, in turn, is coupled to modems or other input/output devices. A background or executive microprocessor is included to manage system configuration and react to failures. The common bus actually comprises a pair of buses and modularity is provided by allowing the number of line processors to be changed by inserting or deleting circuit cards without affecting the operation of other line processors. The communications processor may be redundantly configured by providing an additional arbitrator and additional executive or background processor and information storage and retrieval device such that all common equipment is redundant. On the other hand, the processor can be configured for load sharing wherein a plurality of line processors and one of the executive or background processors operate on one bus under control of an arbitrator operating to and from one of the information storage and retrieval devices, while the other executive or background processor cooperates with a different group of line processors over the other bus under control of the other arbitrator to and from the other information storage and retrieval device.

Claims

1. An information transfer system for transferring information between a common location and a plurality of independently operating data processors over a bi-directional bus operated in a demand assigned mode, said information transfer system including:

an information storage and retrieval device and an arbitrator at said common location, said arbitrator coupling said bi-directional bus to said information storage and retrieval device,

said arbitrator including means for generating a control signal after all said independently operating processors, collectively, either has had, refused or does not require access, and also including clock means for generating a cyclic timing signal having two distinct portions,

a plurality of bus control means, each associated with a different one of said plurality of independently operating data processors, each said bus control means including a control signal input and a control signal output, each said bus control means enabling access to said bi-directional bus by the associated data processor only on receipt of said control signal or a replica thereof,

a clock bus coupled to said clock means for distributing said timing signal to a plurality of said bus control means,

control signal distributing means coupled to said means for generating a control signal for presenting said control signal to be effective at a control signal input of only one of said bus control means, and coupling a control signal output of each of a plurality of said bus control means to be effective at a control signal input of other of said bus control means,

each of said bus control means responsive to the receipt of a control signal or replica thereof at said control signal input for immediately coupling a replica of said control signal to the associated control signal output in the event access to said bus is not required,

or if access to said bus is required, allowing access to said bi-directional bus subsequent to receipt of said control signal or replica thereof and synchronous with said timing signal for one of said distinctive portions and simultaneously with the beginning of said one distinctive portion coupling a replica of said control signal to an associated control signal output.

2. The apparatus of claim 1 in which each of said independently operating data processors include

transmitting means and receiving means each coupled to said bidirectional bus,

said bus control means enabling said transmitting means for the associated data processor for one distinctive portion of said timing signal and enabling said receiving means during another distinctive portion of said timing signal.

3. The apparatus of claim 2 in which said bus control means includes delay means for delaying enablement of said receiver means for a complete period of said timing signal after enablement of said transmitting means ceases.

4. The apparatus of claim 3 in which an arbitrator includes parity checking means for checking parity on information transferred thereto over said bi-directional bus or from said information storage and retrieval device, means in said arbitrator in the absence of a parity error for generating an access complete signal during said second distinctive portion of said timing signal, a further bus coupling said access complete signal to all said plurality of independently operating data processors.

5. The apparatus of claim 4 in which each of said bus control means includes gating means jointly responsive to said delay means and to said access complete signal for enabling said receiving means.

6. The apparatus of claim 5 in which said bus control means includes a bi-stable device set to a distinctive condition when the associated data processor requires access to said bus, and means for halting said data processor until said access is completed.

7. The apparatus of claim 6 in which said independently operating data processor includes parity checking means for checking parity of data received by said receiving means, said bus control means includes logic means responsive to operation of said gating means and to lack of parity error detected at said data processor if any data was received, for generating a signal to reset said bi-stable device and allow continued operation of said processor.

8. The apparatus of claim 2 in which each of said bus control means generates a bus active signal coupled to a further bus common to all said processors and to said arbitrator, which signal is synchronous with the timing signal portion during which an associated transmitting means is enabled, and,

said arbitrator includes receiving means enabled at the conclusion of said first distinctive portion of said timing signal only in the presence of said bus active signal.

9. The apparatus of claim 2 in which each of said bus control means includes means for generating a complete signal either at the time of a bus access or in the event the associated data processor does not require access, a second further bus coupling complete signals from all said plurality of independently operating data processors to said arbitrator,

said means for generating a control signal acting synchronously with said timing signal to generate a control signal each time a complete signal is produced at each of said plurality of independently operating data processors.

10. The apparatus of claim 9 in which said means for generating a control signal includes timing means for timing out a predetermined period, means to initiate said timing means each time said control signal is produced, and means responsive either to a complete signal from all said plurality of independently operating data processors or to completion by said timing means of said predetermined period for generating a further control signal synchronous with said timing signal.

11. The apparatus of claim 2 which includes a second bi-directional bus, and second control signal distributing means,

each of said independently operating data processor including a transmitting and receiving means for each said bi-directional bus,

selecting means for selecting a single one of said buses to which information may be coupled,

said bus control means including a control signal input and output for each said bus,

means responsive to said selecting means for coupling a control signal input and output corresponding to a selected bus to said bus control means and for coupling said control signal input corresponding to an unselected bus to the associated control signal output.

12. The apparatus of claim 11 which further includes:

a second arbitrator in addition to said arbitrator, each operating on a different one of said two bi-directional buses, and

a second information storage and retrieval device in addition to said information storage and retrieval device, each associated with corresponding ones of said arbitrators.

13. The apparatus of claim 12 in which each of said arbitrators generate and couple an end of cycle signal on control lines of their associated bi-directional buses to said independently operating data processors, such that each said data processor receives both said end of cycle signals,

said selecting means including a pair of bi-stable devices each associated with a different one of said buses and responsive to a common selection signal for selecting the bi-directional bus to which said processor will be responsive, each of said bi-stable devices clocked by the corresponding end of cycle signal.

14. The apparatus of claim 1 which further includes an additional independently operating data processor with transmitting and receiving means coupled to said bi-directional bus,

bus access means in said additional data processor for controlling access of said additional data processor to said bi-directional bus,

said bus access means responsive to said timing signal and including bus request signal means for manifesting a request for bus access to said arbitrator,

means in said arbitrator responsive to said bus request signal for granting said request including means for generating a processor clock signal and coupling said clock signal to said additional data processor and for simultaneously generating a gate signal,

said control signal distributing means coupling said gate signal to all said plurality of independently operating data processors,

said bus access means enabling said additional data processor transmitting means responsive to said processor clock signal,

each of said bus control means including gating means responsive to said gate signal to inhibit receipt of said timing signal, whereby an independently operating data processor last receiving said control signal is prevented from accessing said bus means until termination of said gate signal.

15. The apparatus of claim 14 in which said bus access means includes delay means for delaying enablement of said receiving means for a complete cycle of said timing signal after enablement of said transmitting means ceases.

16. The apparatus of claim 1 in which each of said independently operating data processors include a printed circuit card each mounted in a different card slot in a chassis,

each said card including plural control signal inputs and further including a card present signal generator, a card present signal output and a plurality of card present signal inputs, a priority detector coupled to all said card present signal inputs and a multiplexer coupled to all said control signal inputs and controlled by said priority detector,

said control signal distributing means including conductors, each spanning said plurality of slots, each said conductor running from either a card present signal output or a control signal output and connected to card present or control signal inputs of said plurality of cards,

whereby said priority detector locates an adjacent card producing a card present signal and controls said multiplexer to pass a control signal from only said adjacent card.

21. The apparatus of claim 13 wherein said control means enables said receiving means only during said other distinctive portion of said signal.

17. An information transfer system for transferring information between a group of at least three independently operating asynchronous information processing means and a common information storage and retrieval device comprising:

information bus means including plural bi-directional data lines, plural address lines, and plural bus control lines,

said group of independently operating information processing means each coupled to said plural bi-directional data and address lines and at least some of said bus control lines,

arbitrator means coupling said common information storage and retrieval device to said bi-directional data and address lines,

said arbitrator means including bus clock generating means generating a substantially periodic signal having two distinctive portions, said bus clock means coupled through one of said bus control lines to a plurality of said independently operating information processing means, and further including a bus grant signal generating means for producing a bus grant signal,

each of said plurality of independently operating information processing means including,

information transmitting/receiving means coupled to said bi-directional data and address lines of said information bus means, and control means for selectively enabling said information transmitting/receiving means to transmit or receive information from said bus,

said control means coupled to at least some of said bus control lines for enabling said transmitting means to transmit on said information bus means during one distinctive portion of said periodic signal but only in response to receipt of said bus grant signal prior to said one distinctive portion of said periodic signal and, substantially simultaneous with initiation of said transmission, to output a replica of said bus grant signal if the associated information processing means requires access to said information storage and retrieval device, said control means responding to receipt of a bus grant signal to substantially simultaneously therewith output a replica of said bus grant signal if the associated information processing means does not require access to said information storage and retrieval device,

said bus control lines of said bus means including a means coupling said bus grant signal to be effective at only one of said plurality of independently operating information processing means, and further including additional means coupling a bus grant output of said one independently operating information processing means to be effective at only a control means of another independently operating information processing means.

18. The apparatus of claim 17 wherein said information bus means includes a first and second bus, each with said plurality of data, address and control lines,

each of said independently operating information processing means including:

first and second transmitting/receiving means connected respectively to said first and second bus,

selecting means for enabling one of said first or second transmitting/receiving means

said selecting means providing a path from a control line input corresponding to a selected bus to said control means.

19. The apparatus of claim 18 in which said selecting means provides a path from a control signal input to a control signal output corresponding to an unselected bus.

20. The apparatus of claim 17 wherein each of said control means includes a bus grant input and a bus grant output, and said plural bus control lines include a line coupling a bus grant input of a control means other than a control control means associated with said one information processing means.

22. The apparatus of claim 17 wherein said control means includes:

a bi-stable device set to a distinctive condition if the associated information processing means requires access to said information storage and retrieval device,

a second bi-stable device clocked by an edge of said distinctive portion of said periodic signal and set in response to the conjunction of a bus grant signal and a distinctive condition of said bi-stable device

transmit enable means and means for generating a bus grant signal both operative in response to setting of said second bi-stable device,

gating means coupled to said bi-stable device and partially enabled when said bi-stable device is not in said distinctive condition,

said means for generating a bus grant signal coupled to said gating means for generating said bus grant signal substantially simultaneous with receipt of a bus grant signal when said bi-stable device is not in said distinctive condition.

23. The apparatus of claim 22 in which said control means further includes:

timing means initiated by said second bi-stable device when set to count a predetermined number of edges of said periodic signal for resetting said second bi-stable device,

strobe generating means for enabling said receiving means in response to said timing means and in response to information coupled over another of said control lines.

24. The apparatus of claim 23 in which said data processor further includes parity checking means for checking information strobed in by said strobe generating means,

second gating means responsive to said strobe generating means and to said parity checking means for resetting said bi-stable device in the absence of a parity error detected after generation of said strobe.

25. The apparatus of claim 23 in which said arbitrator includes means for generating said information coupled over said another of said control lines including:

checking means for checking information transferred over said information bus means for delivering a one signal in the absence of an error and another signal in the presence of an error.

26. The apparatus of claim 17 in which said

control means includes means for generating a complete signal either when said associated processor has had access to said information bus means or does not require access to said information bus means,

a one of said bus control lines coupled to each said complete signal, and said

bus grant signal generating means produces a bus grant signal when said complete signal is produced by each of said processors.

27. The apparatus of claim 26 wherein said means for generating a complete signal inhibits production of said complete signal on receipt of said bus grant signal.

28. The apparatus of claim 26 in which each said microprocessor includes a local memory, address decoder means for decoding an address and providing an output if said decoded address refers to a location outside of said local memory, and means for manifesting a request for access to said demand assigned information bus means in response to said address decoder output.

29. A method of distributing access to a common bus among a plurality of independently operating data processors each of which can both transmit to and receive from said common bus for the purpose of allowing said data processors to access a common memory device coupled to said bus, the method comprising the steps of:

(1) distributing a cyclic bus timing signal and allowing transmission from any data processor only during a first portion of said timing signal and allowing reception by any said data processor during another portion of said timing signal, exclusive of said first portion

(2) generating a control signal when said processors collectively have had, refused or do not require access and coupling said signal to only one of said data processors,

(3) transmitting from any processor in response to receipt of said control signal, said transmission synchronous with said first distinctive portion and simultaneous with said transmission coupling said control signal to a control signal output, and

(4) coupling said control signal from a control signal output of one data processor to another in a predetermined order.

30. The method of claim 29 in which reception from said common bus is enabled at any data processor that has transmitted but only in a second distinctive portion following a first distinctive portion which itself follows the first distinctive portion during which transmission occurred.

31. The method of claim 29 in which, at any processor not in condition to transmit on reception of said control signal, substituting the following for step (3):

immediately coupling said control signal to said control signal output.

32. The method of claim 29 in which, in addition to said plurality of data processors, there is a further data processor and in which access is distributed to said further data processor only in response to specific requests therefor and then on at most every other cycle of said timing signal.

33. The method of claim 29 in which said step (3) is limited at any processor to a single transmission in any cycle of said timing signal and a transmitting processor is prevented from again transmitting until each other processor has had, refused or does not require access.

34. A communication processor including common memory means,

a bidirectional demand assigned information bus means providing access to said memory means,

a plurality of at least three independently operating asynchronous microprocessors each coupled to said demand assigned information bus means,

arbitrator means and a plurality of bus access means each of said bus access means associated with a different one of said microprocessor for controlling access to said bidirectional demand assigned information bus means by said microprocessors jointly with all other bus access means and said arbitrator means,

memory bus means coupled between said arbitrator and said memory means, said arbitrator means coupled to said bidirectional demand assigned information bus means and to said memory bus means for transferring information between both said bus means,

a plurality of modems, each coupled to a different one of said microprocessors for the transfer of information therebetween and

an executive microprocessor coupled to said bidirectional demand assigned information bus means and to said arbitrator,

a plurality of interface switching means, each interface switching means coupling a modem to a different one of said plurality of independently operating microprocessors,

common interface switching bus,

a group of interface switching means also coupled to said common interface switching bus, logic means in each of said group of interface switching means, and means coupling said logic means to said executive microprocessor, said logic means responsive to controls from said executive microprocessor for coupling information from a modem onto said interface switching bus.

35. The apparatus of claim 34 in which each said microprocessor includes a local memory, address decoder means for decoding an address and providing an output if said decoded address refers to a location outside of said local memory, and means for manifesting a request for access to said demand assigned information bus means in response to said address decoder output.

36. The apparatus of claim 34 wherein said information bus means includes first and second identical information buses and in which each of said microprocessors and said arbitrator each include means responsive to both said buses and selecting means for selecting a one of said buses which said processor or arbitrator will respond to.

37. The apparatus of claim 36 which further includes a second arbitrator means, a second common memory means, a second memory bus means coupled to said second arbitrator means and a second executive microprocessor coupled to both said first and second information buses and to both said arbitrators.

38. The apparatus of claim 34 in which said logic means is responsive to controls from said executive microprocessor for coupling information from said common interface switching bus to an associated microprocessor.

39. An information transfer system for transferring information between a common location and a plurality of at least three independently operating data processors including a bidirectional data and address bus operating in a demand assigned mode, comprising:

bus grant signal generating means at said common location for generating a bus grant signal and for coupling said bus grant signal to a bus grant input of a bus access logic means associated with a single one of said independently operating data processors,

a bus access logic means associated with each of said independently operating data processors for allowing said associated data processor access to said bidirectional data and address bus in response to receipt of said bus grant signal if said associated processor previously requested access to said data and address bus, each said bus access logic means including a bus grant input and a bus grant output,

a control bus, means coupling said control bus to each said bus access logic means for distribution of a clocking signal to each bus access logic means, said control bus including a segmented bus grant conductor with different segments connected from a bus grant output of a bus access logic means to a bus grant input of another bus access logic means, so that each bus grant input is coupled to a bus grant output of a different bus access logic means except for that bus grant input coupled to said bus grant signal generating means,

each said bus access logic means including a complete signal means for producing a distinctive output at an output terminal only when an associated data processor requires access to said data and address bus and for producing a different output at said terminal each time said associated data processor has had access to said data and address bus or does not require such access,

said control bus including first means responsive to said output terminal of each said complete signal means to produce a first output when each said complete signal means does not produce said distinctive output,

said bus grant signal generating means including logic means responsive to said first output of said first means for generating a bus grant signal each time said first means produces said first output.

40. The apparatus of claim 39 in which said bus grant generating means includes timer means responsive to each said bus grant signal to initiate a timing period, and in which said logic means responds to expiration of said timing period to generate said bus grant signal.

41. The apparatus of claim 39 which further includes bus clock generating means for producing a clocking signal coupled to said control bus and therethrough to each said bus access logic means, and wherein each said bus access logic means includes second means responsive to receipt of a bus grant signal to enable transmitters of said associated independently operating data processor, synchronous with said clocking signal and, to simultaneously therewith, output a replica of said bus grant signal if said associated independently operating data processor then requires access to said data and control bus.

42. The apparatus of claim 39 which further includes:

bus clock generating means for producing a clocking signal coupled to said control bus and therethrough to each said bus access logic means, and, wherein each said bus access logic means includes third means responsive to receipt of a bus grant signal to, substantially simultaneously therewith, output a replica of said bus grant signal in the event said associated independently operating data processor does not then require access to said address and data bus.

43. The apparatus of claim 39 which further includes bus clock generating means for producing a clocking signal with rising and falling edges, coupled to said control bus and therethrough simultaneously to each said bus access logic means,

each said bus access logic means includes timing means to respond to said bus grant signal only on a predetermined transition of said clocking signal.