Memory readback check method and apparatus

• US 4,363,125 A
• Filed: 12/26/1979
• Issued: 12/07/1982
• Est. Priority Date: 12/26/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brewer, James A., Lowy, John A.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/106,633
• Time in Patent Office: 1,077 Days
• Field of Search: 371/71, 371/38, 371/51, 364/900, 360/53, 360/31
• US Class Current: 714/824
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements

Abstract

A high speed readback check of data transferred to a cyclic memory before the data source is lost. The cyclic memory is organized into a number of data blocks, each interleaved with or simultaneously accessible with the other data blocks. Thus, a long data record comprises several data blocks and therefore several cycles of the memory. A readback check of data transferred from a source into the memory is accomplished by writing data into one data block in a first cycle, writing data into another block on the second cycle while reading back the first data block and calculating a check character therefrom, continuing through the writing of the entire record, and reading the last block of written data and calculating the check character, and then comparing the calculated check character with a character calculated from the source data to detect any error before the source of the record is lost.

Claims

1. A data storage means for storing data received from a source comprising:

a cyclic memory means having a plurality of data blocks for storing data;

writing means for sequentially writing said received data in said plurality of blocks of said cyclic memory means over a corresponding plurality of cycles of said memory means;

reading means for reading after a one-cycle delay and simultaneously with said writing during ones of said plurality of said cycles, said data written in each said block of said cyclic memory means during the immediately preceding cycle; and

means for comparing said received data and said data read by said reading means to detect any difference therebetween.

2. The data storage means of claim 1 wherein:

said writing means comprises means for sequentially writing said data in a sufficient plurality of said blocks during a corresponding plurality of cycles to store a complete data record; and

said reading means comprises means for sequentially reading said data stored in said plurality of blocks in a like plurality of cycles beginning with the second cycle and ending with the cycle immediately succeeding said corresponding plurality of cycles of said writing means.

3. The data storage means of claim 2 wherein:

said means for comparing additionally comprises signaling means for signaling the detection of any said difference.

4. The data storage means of claim 1 wherein:

said cyclic memory means includes a plurality of data slots, each said data block comprising a set of interleaved said data slots; and

said writing means and said reading means comprise means operable to read and to write different said data blocks comprising different said interleaved data slots of said memory means during the same cycles of said memory means.

5. The data storage means of claim 4 wherein:

said writing means additionally comprises means for sequentially writing said data in a different selected data block comprising a set of said interleaved data slots in each of a successive plurality of cycles to store a data record; and

said reading means additionally comprises means for sequentially reading said data from previously written said data blocks, each comprising a set of said interleaved data slots, in each of a like successive plurality of cycles beginning with the second cycle and ending with the cycle immediately succeeding said successive plurality of cycles of said writing means.

6. The data storage means of claim 5 wherein:

said data slots of said cyclic memory means each comprise the data storage for one bit of data.

7. The data storage means of claim 5 wherein:

said means for comparing additionally comprises signaling means for signaling the detection of any said difference.

8. An input check apparatus for a cyclic memory means having a plurality of data blocks which stores data received from a source in a series of said data blocks over a continuous plurality of cycles of the memory means, one said data block corresponding to one said cycle, and which retrieves said stored data from said series of said data blocks over a like plurality of cycles of the memory means coincident with said continuous plurality of cycles, said input check apparatus comprising:

receive check means for also receiving said received data during said continuous plurality of cycles of said memory means;

read check means for receiving, after a delay of one cycle, said retrieved data corresponding to said received data during said plurality of cycles, beginning with the cycle immediately succeeding the first or said continuous plurality of cycles; and

means responsive to said receive check means and said read check means for comparing said received data and said retrieved data to detect any difference therebetween.

9. An input check apparatus for checking data as stored in a cyclic memory means, said cyclic memory means arranged to store received data in a plurality of data slots in an interleaved fashion in succeeding ones of the cycles thereof, each series of said interleaved data slots in one said cycle comprising a data block, and arranged to retrieve said interleaved stored data by said data blocks over a like plurality of the cycles of the memory means coincident with said succeeding cycles, said input check apparatus comprising:

receive check means for also receiving said received data as stored in said interleaved fashion;

read check means for detecting in said like plurality of said cycles, beginning with the cycle immediately succeeding the first of said succeeding cycles, said retrieved data comprising data blocks corresponding to said interleaved stored data; and

means responsive to said receive check means and said read check means for comparing said received data and said retrieved data to detect any difference therebetween.

10. The input check apparatus of claim 9:

wherein said read check means is additionally arranged to receive a complete data record as received by said memory means and stored thereby in said interleaved fashion over a plurality of cycles, comprising a corresponding plurality of said data blocks, and to generate said first check character therefrom;

additionally including reading means for reading said retrieved data during each of said like plurality of cycles of said memory, said retrieved data comprising said interleaved data stored therein in the immediately preceding cycle; and

said read check means is arranged to receive said data from said reading means and arranged to generate said second check character from the complete data record received from said reading means.