Self-controlled polyphase synchronous motor drive system

• US 4,364,004 A
• Filed: 01/29/1980
• Issued: 12/14/1982
• Est. Priority Date: 01/29/1980
• Status: Expired due to Term

• Current Assignee: Frank J. Bourbeau
• Original Assignee: Frank J. Bourbeau
• Inventors: Bourbeau, Frank J.
• Primary Examiner(s): Witkowski, Stanley J.
• Assistant Examiner(s): Moose, Richard M.
• Application Number:
  US06/116,578
• Time in Patent Office: 1,050 Days
• Field of Search: 318/714, 318/715, 318/716, 318/717, 318/718, 318/719, 318/720, 318/721, 318/722, 318/723, 318/798, 318/799, 318/800, 318/801, 318/802, 318/803, 318/810, 318/811, 318/813
• US Class Current: 318/721
• CPC Class Codes: H02P 25/03 with brushless excitation

Abstract

A self-controlled polyphase synchronous motor drive system having means for producing rotor digital timing signals representative of the position of the rotor relative to the stator, means for producing pulse width modulation control signals wherein the pulse width thereof is responsive to a motor power factor command signal, a plurality of phase control means equal in number to the number of phases of the polyphase stator and responsive to the variable pulse width modulation control signals and including means for producing a modulated analog reference signal from one of two selected stator voltages and means for summing the amplitude modulated analog reference signal with an unmodulated analog reference signal produced from the other of the two selected stator voltages and for comparing the sum thereof with a threshold voltage signal to produce as an output therefrom two motor voltage derived digital timing signals for each phase of the polyphase stator in response to the speed of the motor such that an absence of voltage digital timing signals occurs at zero motor speed and voltage digital timing signals having distortion is produced at low motor speeds and digital gating command signal generating means responsive to the voltage digital timing signals from each of the phase control means and to the rotor digital timing signals for producing digital gating command signals having a leading edge determined by one of the voltage digital timing signals or that of a selected one of the rotor digital timing signals and the width of which is equal to 360 degrees divided by the number of phases of the polyphase stator is shown.

A commutation margin detecting circuit and rotor position sensing circuit are also shown.

Claims

1. A self-controlled polyphase synchronous motor drive system for a synchronous motor having a rotor and a polyphase stator, said stator being adapted to have a polyphase voltage applied thereto, said motor drive system comprising

means for producing rotor digital timing signals which are equal in number to two times the number of phases of the polyphase stator and representative of the position of the rotor relative to the stator;

means for producing pulse width modulation control signals wherein the pulse width thereof is responsive to a motor power factor command signal;

a plurality of phase control means equal in number to the number of phases of the polyphase stator and responsive to the pulse width modulation control signals, each of said phase control means having a selected two of the stator voltages applied as an input thereto and including means for producing a modulated analog reference signal from one of the two selected stator voltages and means for summing the amplitude modulated analog reference signal with an unmodulated analog reference signal produced from the other of the two selected stator voltages and for comparing the sum thereof with a threshold voltage signal to produce as an output therefrom two digital gating timing signals for each phase of the polyphase stator, each of said phase control means being responsive to the speed of a said synchronous motor such that an absence of digital gating timing signals occurs at zero motor speed and digital timing signals having distortion induced therein by changes of current acting on the inductance of the synchronous motor is produced at low motor speeds, said distortion being large compared to the stator voltage at low motor speeds and as the speed of the synchronous motor increases, the stator voltage increases in magnitude such that said distortion becomes smaller in magnitude relative to that of the stator voltage until the stator voltage level reaches a magnitude wherein the sum of the amplitude modulated analog reference signal and unmodulated analog reference signal exceeds the threshold level to produce digital timing signals substantially free of distortion;

a digital gating command signal generating means responsive to the digital gating timing signals from each of the phase control means and to the rotor digital timing signals for producing digital gating command signals wherein at zero motor speed and low motor speeds said digital gating command signal generating means is responsive to said rotor digital timing signals to have the leading edge of the digital gating command signals established by the leading edge of a selected one of the rotor digital timing signals until the motor speed reaches a speed wherein digital gating timing signals substantially free of distortion are produced by the phase control means whereupon the leading edge of the digital gating command signals is determined by one of the leading edges of one of the digital gating timing signals from the phase control means and the leading edge of a selected one of the rotor digital timing signals, whichever occurs first in time, and the width of the digital gating command signals is determined by the phase displacement of successive phases which is equal to 360 degrees divided by the number of phases of the polyphase stator, said digital gating command signals being applied to solid state controlled devices to control the current applied to the stator of the controlled synchronous motor.

2. The self-controlled polyphase synchronous motor drive system of claim 1 wherein the stator voltage responsive means is a voltage transformer.

3. The self-controlled polyphase synchronous motor drive system of claim 1 wherein the variable pulse width producing means includes

a clock generator having an output clocking signal at a predetermined amplitude, frequency and duration;

a ramp generator electrically connected to the clock generator and responsive to the output clocking signals for producing a sawtooth shaped ramp output signal which varies in amplitude between minimum and maximum threshold voltage levels; and

a comparator electrically connected to the ramp generator to receive the sawtooth shaped ramp output signal and to receive a motor power factor command signal representing the power factor of the synchronous motor at a predetermined rotating speed to produce a constant amplitude, pulse width modulated control signal which is applied to the programmable switching means.

4. The self-controlled polyphase synchronous motor drive system of claim 3 wherein the programmable switching means includes logical AND gates having inputs from the comparator and mode signal representative of the motor being in at least one of a braking mode and a motor mode.

5. The self-controlled polyphase synchronous motor drive system of claim 4 wherein the first summing amplifier means are operational amplifiers which are responsive to the output of the AND gates and to a pulse width modulated stator voltage from a selected phase to produce at least one of an amplified modulated stator control voltage and an amplified modulated stator control voltage in response to the motor mode signal.

6. The self-controlled polyphase synchronous motor drive system of claim 5 wherein the second summing amplifier means are operational amplifiers which are responsive to one of the unmodulated stator reference voltage phase and to said motor mode signal for producing at least one of an amplified inverted unmodulated stator reference voltage from the other of the two selected phase and an amplified ummodulated stator reference voltage from the other of the two selected phase in response to the motor mode signal.

7. The self-controlled polyphase synchronous motor drive system of claim 6 wherein the digital responsive means are logical NOR gates, the inputs of which are derived from the digital timing signals from the comparator means and the digital timing signals representative of the rotor position relative to the stator.

8. The self-controlled polyphase synchronous motor drive system of claim 1 wherein the rotor position responsive means includes a variable reluctance transformer having a lobed rotor, an additive series connected primary and opposed series connected secondary winding.

9. The self-controlled polyphase synchronous motor drive system of claim 6 comprising

a starting circuit operatively coupled to the comparator means to enable a controlled synchronous motor to be operated in a rectifier-inverter mode.

10. A self-controlled polyphase synchronous motor digital control system for removing distortion from a control signal applied to solid state controlled devices to control the current applied to the stator of a controlled synchronous motor comprising

means responsive to the stator voltage of a controlled synchronous motor for producing analog load reference voltages representative of the amplitude and frequency of each phase of the stator of a synchronous motor;

means for producing rotor digital timing signals which are equal in number to two times the number of phases of the polyphase stator representative of the position of the rotor relative to the stator;

a plurality of phase control means equal in number to the number of phases of the polyphase stator, each of said phase control means having a selected two of the stator voltages applied as an input thereto and including means for producing a modulated analog reference signal from one of the two selected stator voltages and means for summing the amplitude modulated analog reference signal with an unmodulated analog reference signal produced from the other of the two selected stator voltages and for comparing the sum thereof with a threshold voltage signal to produce as an output therefrom two digital gating timing signals for each phase of the polyphase stator, each of said phase control means being responsive to the speed of a said synchronous motor such that an absence of digital gating timing signals occurs at zero motor speed and digital timing signals having distortion induced therein by changes of current acting on the inductance of the synchronous motor is produced at low motor speeds, said distortion being large compared to the stator voltage at low motor speeds and as the speed of the synchronous motor increases, the stator voltage increases in magnitude such that said distortion becomes smaller in magnitude relative to that of the stator voltage until the stator voltage level reaches a magnitude wherein the sum of the amplitude modulated analog reference signal and unmodulated analog reference signal exceeds the threshold level to produce digital timing signals substantially free of distortion;

a digital gating command signal generating means responsive to the digital gating timing signals from each of the phase control means and to the rotor digital timing signals for producing digital gating command signals wherein at zero motor speed and low motor speeds said digital gating command signal generating means is responsive to said rotor digital timing signals to have the leading edge of the digital gating command signals established by the leading edge of a selected one of the rotor digital timing signals until the motor speed reaches a speed wherein digital gating timing signals substantially free of distortion are produced by the phase control means whereupon the leading edge of the digital gating command signals is determined by one of the leading edges of one of the digital gating timing signals from the phase control means and the leading edge of a selected one of the rotor digital timing signals, whichever occurs first in time, and the width of the digital gating command signals is determined by the phase displacement of successive phases which is equal to 360 degrees divided by the number of phases of the polyphase stator, said digital gating command signals being applied to solid state controlled devices to control the current applied to the stator of the controlled synchronous motor.

11. A commutation margin sensing circuit for producing an analog signal representative of the difference between the trigger angle of a current applied to the polyphase stator of a synchronous motor and the commutation angle of the solid state controlled devices which control the current applied to the polyphase stator comprising

a plurality of threshold comparators equal in number to twice the number of phases of the polyphase stator wherein the comparators are arranged in pairs and each comparator pair is adapted to receive as an input thereto an analog reference signal representative of a voltage between two selected phases of the polyphase stator, each of said pair of comparators being responsive to a first threshold signal applied as an input to one comparator of each comparator pair and second predetermined threshold voltage level applied as an input to the other comparator of each comparator pair

said one of said comparator pair producing as an output therefrom a first and a second successive comparator output pulse for each phase of the voltage applied to the polyphase stator wherein the leading edge and trailing edge of each successive comparator output pulse established each time the amplitude of the stator voltage successively exceeds and then falls below the first threshold voltage level respectively wherein the commutation phase angle is represented by the time between the trailing edge of the first comparator output pulse and the leading edge of the second successive comparator output pulse from said one of said comparator pair, said other of said comparator pair producing as an output therefrom a first and a second successive comparator output pulse for each phase of the voltage applied to the polyphase stator wherein the leading edge and trailing edge of each successive comparator output pulse is established each time the amplitude of the stator voltage successively exceeds and then falls below the second threshold voltage level respectively wherein the commutation phase angle is represented by the time between the trailing edge of the first comparator output pulse and the leading edge of the second successive comparator output pulse from said other one of said comparator pair

said comparator output pulse from said other of said comparator pair occurring later in time than the comparator output pulse from said one of said comparator pair

a plurality of digital gating means equal in number to and operatively coupled to the output of each comparator to receive as one input thereto the comparator output pulse from a selected comparator and to receive as a second input thereto digital gating command signals which are concurrently applied to the solid state controlled devices, said digital gating command signals having a leading edge which is representative of the phase angle at the time the solid state controlled devices are rendered conductive and a width of said digital gating command signals is determined by the phase displacement of successive phases which is equal to 360 degrees divided by the number of phases of the polyphase stator;

each of said digital gating means being adapted to have comparator output pulses from a selected comparator and a selected one of said digital gate command signals applied as an input thereto wherein the trailing edge of the first comparator output pulse and the leading edge of the digital gating command signal occur in coincidence to enable said selected one of the digital gating means to produce as an output therefrom a digital commutation margin pulse having a duration which represents the difference in phase angle between the trigger angle and the commutation angle;

digital pulse selecting means operatively coupled to each of said plurality of digital gating means and responsive to each of said digital commutation margin pulse to produce a series of digital variable width output pulses equal in number to the number of comparators, each of said digital commutation margin pulses having a uniform predetermined amplitude and a width representative of the difference in phase angle between the trigger angle and commutation angle of each phase; and

filtering means operatively coupled to said digital pulse gating means for receiving said series of digital variable width output pulses and averaging the same to produce an analog output signal representative of the commutation margin which is the difference in phase angle between the trigger angle and commutation angle of the controlled synchronous motor.

12. The commutation margin sensing circuit of claim 11 further comprising

nonlinear amplifying means operatively coupled to said filtering means for receiving the commutation margin angle analog output signal as an input thereto and amplifying the same such that, when the magnitude of the commutation margin angle analog output signal is between a maximum level and a lower predetermined level, the nonlinear amplifying means output signal is a constant high level output signal, and, when said magnitude is between zero and said predetermined level, the magnitude of the nonlinear amplifying means output signal is proportional to the magnitude of the commutation margin angle analog output signal which is the input signal to the nonlinear amplifying means.

13. A self-controlled polyphase synchronous motor digital control system for removing distortion from a control signal applied to solid state controlled devices to control the current applied to the stator of a controlled synchronous motor comprising

means responsive to the stator voltage of a controlled synchronous motor for producing analog load reference voltages representative of the amplitude and frequency of each phase of the stator of a synchronous motor;

means for producing rotor digital timing signals which are equal in number to two times the number of phases of the polyphase stator representative of the position of the rotor relative to the stator;

phase control means responsive to the analog load reference voltages for producing a modulated analog reference signal from one of the analog load reference signals and for summing the amplitude modulated analog reference signal with an unmodulated analog reference signal produced from one of the other analog load reference signal and for comparing the sum thereof with a threshold voltage signal to produce as an output therefrom digital gating timing signals, said phase control means being responsive to the speed of a said synchronous motor such that an absence of digital gating timing signals occurs at zero motor speed and digital timing signals having distortion induced therein by changes of current acting on the inductance of the synchronous motor is produced at low motor speeds, said distortion being large compared to the stator voltage at low motor speeds and, as the speed of the synchronous motor increases, the stator voltage increases in magnitude such that said distortion becomes smaller in magnitude relative to that of the stator voltage until the stator voltage level reaches a magnitude wherein the sum of the amplitude modulated analog reference signal and unmodulated analog reference signal exceeds the threshold level to produce digital timing signals substantially free of distortion;

digital gating command signal generating means responsive to the digital gating timing signals from the phase control means and to the rotor digital timing signals for producing digital gating command signals wherein at zero motor speed and low motor speeds, said digital gating command signal generating means substitutes said rotor digital timing signals for the digital gating command signal until the motor speed reaches a speed wherein digital gating timing signals substantially free of distortion are produced by the phase control means whereupon the leading edge of the digital gating command signals is determined by one of the leading edge of one of the digital gating timing signals from the phase control means and the leading edge of a selected one of the rotor digital timing signals, whichever occurs first in time, and the width of the digital gating command signals is determined by the phase displacement of successive phases which is equal to 360 degrees divided by the number of phases of the polyphase stator, said digital gating command signals being applied to solid state controlled devices to control the current applied to the stator of the controlled synchronous motor.

14. An insufficient commutation margin detecting circuit comprising

means responsive to a series of variable pulse width digital signal wherein the variable pulse width signal represents the commutation margin which is the difference between the trigger angle of the stator current with respect to the stator voltage and the angle required for current to transfer from one phase of a motor to another phase of the motor;

a monostable multi-vibrator adapted to have said series of variable pulse width digital signals applied as an input thereto and responsive to the leading edge of said digital signals to produce a controlled digital pulse having a width which represents the minimum width of the variable pulse width digital signal for a sufficient commutation margin angle;

a logical AND gate responsive to said series of variable pulse width digital signals and to said controlled digital pulse to produce an output control digital pulse when the width of a variable pulse width digital signal is less than the width of the controlled digital pulse representing an insufficient commutation angle.

15. A method of blanking digital timing signals having distortion induced therein from spurious signals in a synchronous motor control system at zero motor speed and at low motor speeds with digital timing signals derived from a rotor position sensor comprising the steps of

producing an analog stator reference voltage from a phase shifted stator reference voltage which contains distortions induced therein by current undulations in the stator windings of the motor, said analog stator reference voltage having a positive going portion and a negative going portion each of which contains distortions therein;

comparing the analog stator reference voltage with both a positive threshold voltage and a negative threshold voltage in phase voltage reference comparators to produce output signals having a transition which defines a leading edge, said negative threshold voltage having a value which inhibits passing of a signal by a comparator in response to distortions in the analog stator reference voltage at low speeds to avoid producing a positive stator current when the stator voltage is negative and said positive threshold voltage is responsive to the positive going portion of the analog stator reference voltage to pass a digital timing signal which has a false transition from one binary state to a second binary state induced therein by discontinuities in the positive going portion of the analog stator reference voltage which result in inhibiting of current flow in the stator winding when the stator voltage is positive;

producing digital rotor position timing signals from a rotor position sensor wherein said digital rotor position timing signals have a defined leading edge, a predetermined angular duration and remain at a selected binary state during the predetermined angular duration thereof; and

logically passing the digital rotor position timing signals as the digital timing signals at low motor speeds when the leading edge of the phase voltage reference comparator output signal lags the leading edge of the digital rotor position timing signal until a motor speed is reached such that the leading edge of phase voltage reference comparator output signal is at least one of in phase with and leads the leading edge of the digital rotor position timing signal whereupon the phase voltage reference comparator output signal is logically passed as the digital timing signals.