Offset compensation for switched capacitor integrators

• US 4,365,204 A
• Filed: 09/08/1980
• Issued: 12/21/1982
• Est. Priority Date: 09/08/1980
• Status: Expired due to Term

• Current Assignee: ON Semiconductor Corporation
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Haque, Yusuf A.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US06/185,356
• Time in Patent Office: 834 Days
• Field of Search: 330/9, 330/51, 330/107, 328/127, 328/162, 333/173
• US Class Current: 327/337
• CPC Class Codes: G06G 7/1865 with initial condition setting
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence

Abstract

An integrator circuit utilizing an operational amplifier and switched capacitor elements in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage free from the effects of voltage offsets inherent in operational amplifiers.

Claims

1. An integrator having an integrator input terminal for receiving an input voltage to be integrated and an integrator output terminal, comprising:

an operational amplifier having an inverting input terminal, a non-inverting input terminal connected to a reference potential, and an output terminal, said operational amplifier producing an offset output voltage on said output terminal;

a capacitor connected between the inverting input terminal and the output terminal of said operational amplifier;

switched capacitor means connected between said inverting input terminal and said integrator input terminal; and

means for eliminating the effect of said offset output voltage on said integrator output terminal, said means for eliminating comprising means for storing a stored voltage equal to said input voltage to be integrated minus said offset output voltage and means for applying said stored voltage to said inverting input terminal of said operational amplifier, whereby said input voltage is integrated and said offset output voltage is not integrated.

2. Structure as in claim 1 further comprising an offset voltage source other than said operational amplifier, providing a voltage equal to said output offset voltage of said operational amplifier, wherein said switched capacitor means includes a switched capacitor having a first and a second plate, and wherein said means for eliminating first causes said switched capacitor to be charged to a voltage equal to said input voltage to be integrated minus said output offset voltage of said operational amplifier as provided by said offset voltage source by first connecting said first plate to the input voltage and connecting said second plate to said offset voltage source and then causing said first plate to be connected to said reference potential and said second plate to be connected to the inverting input terminal of said operational amplifier.

3. Structure as in claim 2 wherein said offset voltage source is a sample and hold circuit comprising:

a storage capacitor having a first and a second plate, said second plate connected to said reference potential;

switch means for connecting the output terminal of said operational amplifier to said first plate of said storage capacitor only when the voltage on said output terminal of said operational amplifier is equal to said offset output voltage;

an offset buffer amplifier having an input lead and an output lead, said input lead connected to said storage capacitor first plate;

whereby a constant voltage equal to the offset output voltage of said operational amplifier is available on said output lead of said offset buffer amplifier during the complete integration cycle.

4. Structure as in claim 3 wherein said integrator further includes an additional buffer amplifier having characteristics closely matched to the characteristics of said offset buffer amplifier, and wherein an offset voltage difference between the output voltage and the input voltage of said offset buffer amplifier is substantially equal to an offset voltage difference between the output voltage and the input voltage of said additional buffer amplifier, and wherein said additional buffer amplifier has an input lead connected to said output terminal of said operational amplifier and an output lead connected to said integrator output terminal;

whereby the effect on the output voltage of said integrator due to said offset voltage of said offset buffer amplifier is eliminated by the presence of said additional buffer amplifier.

5. An integrator having an input terminal for receiving an input voltage to be integrated and an output terminal, comprising:

an operational amplifier having an inverting input lead, a noninverting input lead connected to a reference voltage, and an output lead, said operational amplifier producing a first offset output voltage on said output lead;

a first buffer amplifier having an input lead connected to said output lead of said operational amplifier and an output lead connected to said output terminal of said integrator, said first buffer amplifier producing a second offset output voltage on said output lead of said first buffer amplifier;

a second buffer amplifier having an input lead and an output lead, said second buffer amplifier producing a third offset output voltage on its output lead;

a capacitor connected between said inverting input lead of said operational amplifier and said output terminal of said integrator;

first switch means connected between said inverting input lead of said operational amplifier and said output terminal of said integrator;

second switch means connected between said output lead of said operational amplifier and said input lead of said second buffer amplifier;

a storage capacitor connected between said input lead of said second buffer amplifier and said reference voltage; and

switched capacitor means connected between said input terminal of said integrator and said inverting input lead of said operational amplifiers, said switched capacitor means including

a switched capacitor having a first and a second plate;

third switch means connected between said first plate and said input terminal of said integrator;

fourth switch means connected between said first plate and said reference voltage;

fifth switch means connected between said second plate and said output lead of said second buffer amplifier;

sixth switch means connected between said second plate and said inverting input lead of said operational amplifier;

wherein, during an initialization period,

said first and second switch means are closed and said sixth switch means is open, thereby generating an integrator offset voltage on said output terminal of said integrator equal to the sum of said first and said second offset output voltages;

said storage capacitor is charged to a voltage equal to said first offset output voltage;

said second buffer amplifier generates on said output lead of said second buffer amplifier a voltage equal to said integrator offset voltage; and

wherein said first and second switch means are open during periods other than said initialization period and said input voltage is integrated by

closing said third and said fifth switch means and opening said fourth and said sixth switch means, thereby storing on said switched capacitor a voltage equal to said input voltage minus said integrator offset output voltage; and

opening said third and said fifth switch means and closing said fourth and said sixth switch means, thereby integrating said input voltage and preventing the integration of said integrator offset output voltage.

6. Structure as in claim 5 wherein said switch means are transistors.

7. Structure as in claim 6 wherein said transistors are MOS transistors.