Industrial control system with distributed computer implemented logic

• US 4,365,297 A
• Filed: 12/29/1980
• Issued: 12/21/1982
• Est. Priority Date: 12/29/1980
• Status: Expired due to Term

• Current Assignee: HF Controls LP
• Original Assignee: Fornex Engineering Company
• Inventors: Grisham, James S. Jr.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/221,328
• Time in Patent Office: 722 Days
• Field of Search: 364/200 MS
• US Class Current: 710/8
• CPC Class Codes: G05B 19/052 Linking several PLC's
• CPC Class Codes: G05B 19/4181 characterised by direct numerical control [DNC]
• CPC Class Codes: G05B 2219/25337 Sbc single board computer, stand alone
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An industrial control system is disclosed in which various on/off or other binary functions of an industrial process are each controlled by a separate single board computer. Each single board computer is provided with a simplified system whereby the user can interconnect a logic system between input ports and output ports of the computer to control the setting of the binary data at the output ports in accordance with the selected logic system in response to the data applied to the input ports with the output ports being connected to control the on/off and binary functions in the system. The logic functions are implemented in each single board computer by use of an applications program and a patch panel program. In the applications program, the system responds to input data in a flag memory and sets output flags in the flag memory in accordance with each possible logic function that might be used in the system. In the patch panel portion of the program, the input flags are set and the data at the I/O ports are set in accordance with connection specified by the storing of specific addresses in a patch panel memory.

Claims

1. A computer system for setting a plurality of output signals in accordance with input data and logic functions operating upon said data in accordance with interconnections directed by the user of said computer system comprising:

a first memory having a set of logic input locations for storing input data and a set of logic output locations to store output data,

program storage means containing program instructions including an applications set of instructions and a patch panel set of instructions,

computer means to obtain and execute said instructions in a repeated program sequence alternately cycling through said patch panel set of instructions and said applications set of instructions,

said applications set of instructions causing said computer means to carry out a multiplicity of logic functions on the data stored in said logic input locations and to store data in said logic output locations in accordance with said data in said logic input locations and the logic functions performed on the data in said logic input locations, each of said logic functions having at least one input location assigned exclusively thereto and one logic output location assigned exclusively thereto,

a plurality of I/O ports for receiving input data and for storing output data to set output conditions at said I/O ports,

a patch panel memory having a plurality of memory locations, each memory location having a FROM section and a TO section adapted to store addresses of said I/O ports, said logic input locations, and said logic output locations, whereby the user of the system can specify connections by the addresses stored in said patch panel memory from said I/O ports to the inputs of said logic functions, from the outputs of said logic functions to said I/O ports, and from the output of said logic functions to the inputs of said logic functions,

said patch panel set of instructions causing said computer means to read out the addresses stored in sequential memory locations of said patch panel memory in sequence and to read the data selected by the addresses stored in the FROM sections and to store data in accordance therewith at the addresses selected by the corresponding T0 sections;

whereby said computer means by alternately cycling through said patch panel set of instructions and said applications set of instructions will perform logic functions on the input data at said I/O ports in accordance with the interconnections of said logic functions specified by the user in said patch panel memory and store data at said I/O ports in accordance with the logic functions performed on said input data.

2. A computer system as recited in claim 1, wherein a plurality of said logic functions are AND gates, each of which has a single input flag as its sole logic input location, said program including a set of instructions to cause said computer means to set a one at the input flag at each of said AND gates prior to each time said computer means begins execution of said patch panel set of instructions and after said computer means completes execution of said applications set of instructions, set patch panel set of instructions causing said computer means to set to zero the input flag of each AND gate selected by an address read from a TO section of said patch panel memory if the address in the corresponding FROM section in said patch panel memory selects a storage location containing zero and to leave the input flag of such AND gate unchanged if the address in the corresponding FROM section selects a storage location containing one.

3. A computer system as recited in claim 1, wherein a plurality of said logic functions are OR gates each having a single input flag as its sole logic input location, said program including a set of instructions to cause said computer means to set a zero in the input flag of each of said OR gates prior to each time said computer means begins execution of said patch panel set of instructions and after said computer means completes execution of said applications set of instructions, said patch panel set of instructions causing said computer means to set to one the input flag of each OR gate selected by an address read from a TO section of said patch panel memory if the address in the corresponding FROM section in said patch panel memory selects a storage location containing a one and to leave the input flag of such OR gate unchanged if the address in the corresponding FROM section selects a storage location containing a zero.

4. A computer system as recited in claim 1, wherein a plurality of said logic functions are OR and AND gates each having a single input flag as its sole logic input location, said program including a set of instructions to cause said computer means to set a one in the input flag of each of said AND gates and a zero in the input flag of each of said OR gates prior to each time said computer means begins execution of said patch panel set of instructions and after said computer means completes execution of said applications set of instructions, set patch panel set of instructions causing said computer means to set to zero the input flag of each AND gate selected by an address read from a TO section of said patch panel memory if the address in the corresponding FROM section in said patch panel memory selects a storage location containing zero, and to leave the input flag of such AND gate unchanged if the address in the corresponding FROM section selects a storage location containing one, and causing said computer means to set to one the input flag of each OR gate selected by an address read from a TO section of said patch panel memory if the address in corresponding FROM selection in said patch panel memory selects the address of a storage location containing a one and to leave the input flag of such OR gate unchanged if the address in the corresponding FROM section selects a storage location containing a zero, said patch panel set of instructions causing said computer means upon reading out of the TO section of said patch panel memory the address of a logic input location which is not the input flag of a simple AND gate or a simple OR gate to store at such memory location the data read out from the address selected by the corresponding FROM section in said patch panel memory.

5. A computer system as recited in claim 1, wherein each of said logic input locations in said first memory and each of said logic output locations in said first memory separately selectable by addresses stored in said patch panel memory are flags, each capable of storing one bit of data and each of said I/O ports separately selectable by addresses stored in said patch panel memory is operable to receive or store one bit of data.

6. A computer system as recited in claim 1 operative as an industrial control system which includes a plurality of control devices connected to some of said I/O ports and controlled in accordance with the data stored at such I/O ports and including means to apply input signals to said I/O ports in accordance with operating conditions of said industrial control system.

7. A computer system as recited in claim 6, wherein there is means to apply an input signal to one of said I/O ports in accordance with the condition of a manual operable control means.

8. A distributed control system for controlling a plurality of control devices comprising:

a plurality of control computers each connected respectively to individual ones of a plurality of control devices for providing control thereto, each of said control devices connected to its respective control computer through I/O ports;

said computers being connected to one another and to a central supervisory computer through a data highway, said supervisory computer being operable to selectively monitor the function of each of said control computers,

each of said control computers having;

a first memory having a set of logic input locations for storing input data and a set of logic output locations to store output data,

program storage means containing program instructions including an applications set of instructions and a patch panel set of instructions,

a patch panel memory having a plurality of memory locations, each memory location having a FROM section and a TO section adapted to store addresses of said I/O ports, said logic input locations and said logic output locations, and

computer means to obtain and execute said instructions in a program sequence alternately cycling through said patch panel set of instructions and said applications set of instructions,

said applications set of instructions causing said computer means to carry out logic functions on the data stored in said logic input locations and to store data in said logic output locations in accordance with the data in said logic input locations and the logic functions performed on the data in said logic input locations, each of said logic functions having at least one logic input location assigned exclusively thereto and one logic output location assigned exclusively thereto,

said patch panel set of instructions causing said computer means to read out the addresses stored in sequential memory locations of said patch panel memory in sequence and to read the data selected by the address stored in said FROM sections and to store data in accordance therewith at the addresses selected by the corresponding TO sections;

the applications set of instructions in the program storage means of each control computer causing the computer means of said control computer to carry out all of the logic functions necessary to effect control of each of the control devices connected to the I/O ports of all of said control computers,

whereby the computer means of each of said control computers by alternately cycling through said patch panel set of instructions and said applications set of instructions will perform logic on the input data at the I/O ports of such control computer in accordance with the interconnections of said logic functions specified by the user in the patch panel memory of such control computer and control said control devices connected to said I/O ports in accordance with the logic functions performed on said input data.