Power down detector

• US 4,366,560 A
• Filed: 09/22/1980
• Issued: 12/28/1982
• Est. Priority Date: 09/22/1980
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: McDermott, Mark W., Feldman, Neil B.
• Primary Examiner(s): Stellar, George G.
• Application Number:
  US06/189,974
• Time in Patent Office: 827 Days
• Field of Search: 307/200 A, 307/200 B, 307/238.3, 307/279, 307/291, 307/362, 307/363, 307/593, 307/594, 340/663, 361/92, 365/95, 365/154, 365/228
• US Class Current: 365/228
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.

Claims

1. A circuit for detecting supply voltage variations thereto comprising,

(a) binary means for indicating the circuit to be in a first or second state,

(b) means associated with said binary means for causing said binary means to assume a first of said first or second states upon application of a source of power to said circuit,

(c) means coupled to said binary means for forcing said binary means to the second of said first or second states, and

(d) further means coupled to said binary means and to said source of power for causing said binary means to reassume said first state in the event of reduction of voltage from said source of power to said circuit.

2. A circuit as set forth in claim 1 wherein said binary means is a flip-flop.

3. A circuit as set forth in claim 1 wherein said binary means is a memory cell.

4. A circuit as set forth in claim 1 wherein said binary means is a pair of cross-coupled transistors.

5. A circuit as set forth in claim 4 wherein said means for causing said binary means to assume a first state comprises a pair of load devices each connected to one of said pair of cross-coupled transistors, and in said load devices are unequal in gain.

6. A circuit as set forth in claim 5 wherein the connection of each load to its respective transistor defines a node, and further comprising means connected between said nodes whereby a reduction in voltage from said source of power causes a coupling of said nodes.

7. A circuit for detecting power variations comprising:

(a) a first transistor and a second transistor connected in a cross-coupled configuration;

(b) said first transistor having a first load coupled thereto at a first node and to a power supply potential;

(c) said second transistor having a second load coupled thereto at a second node and to a power supply potential, said second load having a relatively higher gain than said first load, thereby causing the circuit to assume, upon application of power thereto, a first state;

(d) means for applying a signal to said circuit, said signal causing the circuit to assume a second state;

(e) a third transistor coupled between said first and second nodes and having an electrode coupled to said power supply potential;

(f) whereby a reduction in power supply potential causes the circuit to revert to said first state.

8. A circuit as set forth in claim 7 wherein said reversion to said first state is due to charge transfer between said first and second nodes.

9. A circuit as set forth in claim 7 wherein said first transistor and said second transistor are of a first polarity type and said third transistor is of opposite polarity type.

10. A circuit as set forth in claim 7 wherein said first load is a passive load and said second load is an active load.