Sine wave generator for different frequencies

• US 4,368,432 A
• Filed: 11/12/1980
• Issued: 01/11/1983
• Est. Priority Date: 11/12/1980
• Status: Expired due to Term

• Current Assignee: Siemens Corp. (Siemens AG)
• Original Assignee: Siemens Corp. (Siemens AG)
• Inventors: Levy, Allan
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US06/206,256
• Time in Patent Office: 790 Days
• Field of Search: 328/14, 340/347 M, 364/721
• US Class Current: 327/107
• CPC Class Codes: H03K 4/026 using digital techniques
• CPC Class Codes: H04M 1/505 signals generated in digital form

Abstract

A frequency oscillator for generating a square wave output pulse train is connected via a frequency divider circuit to a binary shift register which is designed as a divide-by-n counter with m counter stages, wherein m=n/2. Each stage is associated with an output. A resistor network is composed of m rated resistors each of which resistors is connected to a respective register output and in common to an input of a low-pass filter network forming the output circuit. The rating of the resistors is such that an k-th resistor associated with the k-th output of the shift register has the value ##EQU1## wherein R is a reference resistance value;

k is a positive integer from 1 through m;

C is 1/2 if m is an odd number; and

C is 0 if m is an even number.

Sine wave forms of different frequencies may be selectively chosen if the frequency divider circuit is provided with parallel inputs which are associated with different dividing ratios and are selectively coupled to the input of the binary shift register.

Claims

1. A sine wave generator composed of digital circuits comprising:

(a) a high frequency oscillator for generating a square wave output pulse train;

(b) a frequency divider circuit being composed of

a first ripple carry binary counter having a data input and an output, and being symmetrically arranged between positive and negative supply voltage, said data input being connected to said output of said square wave oscillator; and

a second shift register including Johnson-counter stages being symmetrically arranged between positive and negative supply voltage, having a data input, a clock input connected to said output of said binary counter and having parallel outputs, one of said parallel outputs forming an output of said frequency divider network;

(c) a binary shift register being designed as a divide-by-n counter and having m counter stages, wherein m=n/2, said shift register having a clock input connected to said output of said frequency divider circuit and having m outputs each associated with a respective one of said counter stages;

(d) a resistor network being composed of m rated resistors having first and second taps and being arranged in parallel with said first taps connected together, and each of said second taps being connected to a respective one of said outputs of said shift register, wherein the rating of said resistors is such that an k-th resistor associated with the k-th output of said shift register has the value ##EQU5## and wherein k is a positive integer from 1 through m;

R is a reference resistance value;

C=1/2 if m is an odd number; and

C=0 if m is an even number; and

(e) a low-pass filter network having an input and an output, said network input being connected to said commonly connected first taps of said resistors and said network output forming the sine wave signal output of said generator.

2. The sine wave generator as recited in claim 1, wherein said shift register is composed of Johnson-counter stages and is connected to identical positive and negative supply voltages whereby said shift register is operated in a manner which is balanced with respect to a reference level of zero volts.

3. The sine wave generator as recited in claim 2, comprising a further resistor arranged between said commonly connected first taps of said resistor network and ground.

4. The sine wave generator as recited in claim 1, wherein the low-pass filter network further comprises:

(e1) an operational amplifier having a positive and a negative input and an output, said output being connected to said output of said sine wave generator;

(e2) a voltage divider composed of two further resistors being connected in series via a connector tap, said voltage divider being arranged between said input of said filter network and said positive input of said operational amplifier;

(e3) a first capacitor coupled to said positive input of said operational amplifier and connected to ground;

(e4) a second capacitor inserted between said connector tap and said negative input of said operational amplifier; and

(e5) a load resistor arranged between positive supply voltage on one hand and said negative input and said output of said operational amplifier on the other hand.

5. The sine wave generator as recited in claim 4, wherein said low-pass filter network further comprises a by-pass capacitor arranged between said output of said operational amplifier and ground.

6. The sine wave generator as recited in claim 1, wherein said high frequency oscillator further comprises:

(a1) a parallel circuit including a quartz crystal, a further resistor and a first inverter; and

(a2) a second inverter being arranged between said parallel circuit and said output of said oscillator in a series orientation with respect to said first inverter.

7. The sine wave generator as recited in claim 1, wherein the second shift register further comprises:

(b3) an output network including a plurality of AND-gates each having two inputs and an output, said inputs of each of said AND-gates being connected to two neighboring outputs of said shift register and each of said outputs of said AND-gates forming an additional divider output; and

(b4) a feedback line from said output of said frequency divider circuit to said data input of said second shift register.

8. The sine wave generator as recited in claim 1, further comprising means for selectively connecting one of said parallel frequency divider outputs to said clock input of said first shift register.

9. The sine wave generator as recited in claim 8, wherein said connecting means further comprise a set of jumpers, each of said jumpers being associated with a respective one of said outputs of said frequency divider circuit for coupling a respective one of said outputs of said second shift register to said clock input of said first shift register.

10. The sine wave generator as recited in claim 8, wherein said connecting means further comprise a set of transistor switches, each having two main electrodes and a control electrode, each of said switches arranged by said main electrodes between a respective one of said parallel outputs of said second shift register and said input of said first shift register;

and a selector circuit including a gang switch having an input and outputs, each of said outputs of said gang switch connected to a respective one of said control electrodes; and

a direct current voltage source connected to said input of said gang switch.