Self-aligned, flip-chip focal plane array configuration

• US 4,369,458 A
• Filed: 07/01/1980
• Issued: 01/18/1983
• Est. Priority Date: 07/01/1980
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Westinghouse Electric Corporation (Paramount Global (f/k/a ViacomCBS Inc.))
• Inventors: Thomas, Richard N., Sopira, Michael M.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Carroll, J.
• Application Number:
  US06/165,158
• Time in Patent Office: 931 Days
• Field of Search: 357/30, 357/40, 357/65, 357/15, 357/24 LR
• US Class Current: 257/226
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14881 of the hybrid type
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 31/022408 : for devices characterised by at least one potential jump barrier or surface barrier

Abstract

A focal plane array including a first integrated circuit for infrared radiation (IR) detection and a second integrated circuit for signal processing is assembled in a flip-chip structural configuration. Each integrated circuit includes an array of metallic contacts on a surface thereof for interconnection in the flip-chip arrangement. The contact array of the IR detector includes a substantially greater number of contacts than the contact array of the signal processor. Consequently, it is not a prerequisite to precisely align the two integrated circuits in a one-to-one contact relationship for the flip-chip bonding operation therebetween. Thus, each metallic contact of the signal processor may be roughly aligned and bonded to a corresponding group of metallic contacts of the IR detector array without altering significantly the operation of the overall focal plane array as long as at least one metallic contact of the IR detector array is included in each corresponding contact group. As a result of this structural improvement, a method of batch-fabricating a plurality of high-density focal plane arrays may be accomplished quite expeditiously.

Claims

1. A flip-chip interconnected focal plane array circuit configuration comprising:

a first integrated circuit for signal processing having a first array of electrical signal storage cells, each cell having an injection site and a metallic cell contact disposed at said site to provide electrical connection thereto; and

a second integrated circuit for radiation detection having a substrate with a first side conditioned for accepting a radiation image thereon, and a second side, opposite said first side, including a second array of metallic detector contacts disposed on the surface thereof, said second array having a greater density of contacts than said first array for substantially equal surface areas, said metallic detector contacts being smaller in physical size than said metallic cell contacts;

said first and second integrated circuits being interconnected in a flip-chip configuration with each metallic cell contact of said first circuit being bonded physically to a corresponding group of metallic detector contacts of said second circuit, each corresponding bonded group of metallic detector contacts defining a corresponding volume in the substrate of said second integrated circuit and an associated surface area on the first side thereof, whereby in operation, the radiation image accepted by the first side of the second circuit is divided into picture elements in accordance with the defined associated surface areas and electrical signals representative of the radiation image elements are photogenerated in the corresponding volumes of the second circuit, the photogenerated electrical signals being conducted to the correspondingly associated cells of the first circuit, through their metallic cell and detector contact bondings, to form compositely in the storage cell array thereof an electrical representation of the radiation image accepted by the second circuit.

2. The flip-chip circuit configuration in accordance with claim 1 wherein the second integrated circuit is an infrared radiation detector.

3. The flip-chip circuit configuration in accordance with claim 2 wherein the substrate of the second integrated circuit comprises an extrinsically doped semiconductor material having the properties of detecting infrared radiation in a predetermined wavelength window and of converting said detected infrared radiation to an electrical signal elementally by photoconductive techniques, said photoconductive radiation detector elements being defined by the cellular bonded groups of metallic detector contacts.

4. The flip-chip circuit configuration in accordance with claim 3 wherein the metallic cell and detector contacts are primarily gold.

5. The flip-chip circuit configuration in accordance with claim 2 wherein the substrate of the second integrated circuit comprises an intrinsic material having the properties of detecting infrared radiation in a predetermined wavelength window and of converting said detected radiation to an electrical signal elementally by photovoltaic techniques, said photovoltaic radiation detector elements being defined by the cellular bonded groups of metallic detector contacts.

6. The flip-chip circuit configuration in accordance with claim 5 wherein the metallic cell and detector contacts are primarily indium.

7. The flip-chip circuit configuration in accordance with claim 3 or 5 wherein the first integrated circuit comprises a charge coupled device (CCD) having a first parallel input cell array and accompanying cell injection metallic contacts.

8. The flip-chip circuit configuration in accordance with claim 1 wherein the first array of metallic cell contacts is configured on a surface of the first integrated circuit as a two dimensional array of rows and columns having center-to-center spacings of a first predetermined distance;

and wherein the second array of metallic detector contacts is configured on the surface of the second side of the second integrated circuit as a two-dimensional array of rows and columns having center-to-center spacings of a second predetermined distance which is substantially less than said first predetermined distance.

9. The flip-chip circuit configuration in accordance with claim 1 wherein the metallic detector contacts are metal pads of a first height and first maximum cross-sectional area, and wherein the metallic cell detectors are metal bumps of a second height and second maximum cross-sectional area, said second height being substantially greater than said first height and said second maximum area being substantially greater than said first maximum area.

10. The flip-chip circuit configuration in accordance with claim 1 wherein the physical bonding connection between the metallic cell and detector contacts is one of a thermal compression bond.