Self-clocking data transmission system

• US 4,369,516 A
• Filed: 09/15/1980
• Issued: 01/18/1983
• Est. Priority Date: 09/15/1980
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Byrns, John P.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/187,303
• Time in Patent Office: 855 Days
• Field of Search: 375/38, 375/110, 370/85, 370/91, 370/100, 371/68-70, 360/39, 360/40, 360/48, 360/49, 455/608, 364/900 MS File
• US Class Current: 375/359
• CPC Class Codes: H04L 1/02 by diversity reception
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals

Abstract

A data transmission system is described where data signals are bidirectionally transmitted between a data transmitter and a plurality of data receivers in a self-clocking bit streams carried on true data and complement data signal lines and a non-return-to-zero (NRZ) bit streams on a return data signal line. According to an inventive data transmission scheme, data signals are transmitted by the data transmitter by utilizing the four possible two-bit binary states of the true data and complement data signal lines. Of the four two-bit binary states, a word state is provided before and after the data signal and a one state or zero state followed by a bit state is provided for each bit of the data signal. The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal. In response to the bit clock signal, the NRZ data signal is serially shifted into a register while a previously parallel loaded return data signal is shifted out of the register and applied to the return data signal line. The inventive data transmission scheme is self-clocking and highly immune to speed and timing variations in the transmission. The inventive data transmission may be advantageously utilized for data transmission in many different data transmission systems, such as computer systems for data transmission between a microprocessor and peripheral units and control systems for data transmission between a central control station and geographically remote stations.

Claims

1. A method of serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said method comprising the steps of:

(a) generating a first binary state of the first and second signals before and after the data signal;

(b) generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and

(c) generating the second binary state of the first and second signals between successive bits of the data signal.

2. The method according to claim 1, further including the step of repeating steps (b) and (c) for transmitting subsequent data signals.

3. The method according to claim 1, further including the step of generating a clock signal having a dynamically varying frequency, said step (b) generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.

4. The method according to claim 1, further including the step of generating a clock signal having a frequency varying over a predetermined range of frequencies, said step (b) generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.

5. The method according to claim 1, further including the step of generating a clock signal having a predetermined frequency, said step (b) generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.

6. A method of serially transmitting an address signal and a data signal from a signal source by means of first and second binary signals, the address signal and data signal each including a plurality of bits having a binary zero state or a binary one state, said method comprising the steps of:

(a) generating a first binary state of the first and second signals before the first bit of the address signal and after the last bit of the data signal;

(b) generating for each bit of the address signal a second binary state of the first signal and the first binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary one state;

(c) generating for each bit of the data signal the second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and

(d) generating the second binary state of the first and second signals between successive bits of the data signal.

7. The method according to claim 6, further including the step of repeating steps (d) and (e) for transmitting subsequent data signals.

8. The method according to claim 6, further including the step of generating a clock signal having a dynamically varying frequency, said steps (b) and (d) generating the respective binary states of the first and second signals for each bit in response to the clock signal.

9. The method according to claim 6, further including the step of generating a clock signal having a frequency varying over a predetermined range of frequencies, said steps (b) and (d) generating the respective binary state of the first and second signals for each bit in response to the clock signal.

10. The method according to claim 6, further including the step of generating a clock signal having a predetermined frequency, said steps (b) and (d) generating the respective binary states of the first and second signals for each bit in response to the clock signal.

11. Apparatus for serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said apparatus comprising:

first means for generating a first binary state of the first and second signals before and after the data signal;

second means for generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating a first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and

said second means generating the second binary state of the first and second signals between successive bits of the data signal.

12. The data transmitting apparatus according to claim 11, further including means for generating a clock signal, said second generating means generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.

13. The data transmitting apparatus according to claim 12, further including means for providing a strobe signal and means responsive to the strobe signal for storing a data signal, said second generating means responsive to the data signal stored in the storing means for generating the respective states of the first and second signals.

14. Apparatus for receiving a data signal from first and second binary signals serially transmitted by a signal source, the data signal including a plurality of bits each having a binary zero state or a binary one state, the first and second signals having a first binary state before and after the data signal, the first signal having a second binary state and the second signal having a first binary state for data signal bits having a binary zero state, the first signal having a first binary state and the second signal having a binary state for data signal bits having a binary one state, and the first and second signals having a second binary state between successive data signal bits, said receiving apparatus comprising:

first means responsive to the second binary state of the first and second signals for generating a clock signal;

second means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and storing an output signal having a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and

third means coupled to the first means and second means for storing the second means output signal in response to the clock signal.

15. The data receiving apparatus according to claim 14, further including a signal source for providing a return data signal having a plurality of binary bits, and means responsive to the clock signal for generating for successive bits of the return data signal a corresponding binary state of a return signal.

16. The data receiving apparatus according to claim 15, further including means for generating a pulsed binary state of the return signal line to indicate that a return data signal is available for transmission.

17. A system for serially communicating data signals, each including a plurality of bits each having a binary zero state or a binary one state, between a transmitting unit and at least one receiving unit intercoupled by first and second binary signals, said system comprising:

a transmitting unit for transmitting a data signal, including;

a signal source for providing a data signal;

first means for generating a first binary state of the first and second signals before and after the data signal;

second means for generating for each bit of the data signal a second binary state of the first signal and a first binary state of the second signal for a bit having a binary zero state, and the first binary state of the first signal and a second binary state of the second signal for a bit having a binary one state; and

said second means generating the second binary state of the first and second signals between successive bits of the data signal; and

a receiving unit for receiving a data signal transmitted by the transmitting unit, including;

third means responsive to the second state of the first and second signals for generating a clock signal;

fourth means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and

fifth means coupled to the third means and fourth means for storing successive binary states of the fourth means output signal in response to the third means clock signal.

18. The data communication system according to claim 17, wherein said transmitting unit further includes sixth means for generating a clock signal, said second means generating the respective binary states of the first and second signals for each bit in response to the clock signal.

19. The data communication system according to claim 18 further including a binary return signal between the transmitting unit and receiving unit, said receiving unit further including a signal source for providing a return data signal having a plurality of binary bits, and seventh means responsive to the third means clock signal for generating for successive bits of the return data signal a corresponding binary state of the return signal, and the transmitting unit further including eighth means coupled to the return signal for storing in response to the sixth means clock signal successive binary states of the return signal.

20. The data communication system according to claim 19, wherein said receiving unit further includes nineth means for generating a pulsed binary state of the return signal to indicate that a return data signal is available for transmission, said transmitting unit including tenth means coupled to the return signal for detecting said pulsed binary state and enabling the transmitting unit to transmit a data signal.

21. The data communication system according to claim 19 or 20, including a plurality of said receiving units each coupled to the first and second signals and the return signal.