Self-clocking data transmission system
First Claim
1. A method of serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said method comprising the steps of:
- (a) generating a first binary state of the first and second signals before and after the data signal;
(b) generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and
(c) generating the second binary state of the first and second signals between successive bits of the data signal.
1 Assignment
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Accused Products
Abstract
A data transmission system is described where data signals are bidirectionally transmitted between a data transmitter and a plurality of data receivers in a self-clocking bit streams carried on true data and complement data signal lines and a non-return-to-zero (NRZ) bit streams on a return data signal line. According to an inventive data transmission scheme, data signals are transmitted by the data transmitter by utilizing the four possible two-bit binary states of the true data and complement data signal lines. Of the four two-bit binary states, a word state is provided before and after the data signal and a one state or zero state followed by a bit state is provided for each bit of the data signal. The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal. In response to the bit clock signal, the NRZ data signal is serially shifted into a register while a previously parallel loaded return data signal is shifted out of the register and applied to the return data signal line. The inventive data transmission scheme is self-clocking and highly immune to speed and timing variations in the transmission. The inventive data transmission may be advantageously utilized for data transmission in many different data transmission systems, such as computer systems for data transmission between a microprocessor and peripheral units and control systems for data transmission between a central control station and geographically remote stations.
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Citations
21 Claims
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1. A method of serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said method comprising the steps of:
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(a) generating a first binary state of the first and second signals before and after the data signal; (b) generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and (c) generating the second binary state of the first and second signals between successive bits of the data signal. - View Dependent Claims (2, 3, 4, 5)
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6. A method of serially transmitting an address signal and a data signal from a signal source by means of first and second binary signals, the address signal and data signal each including a plurality of bits having a binary zero state or a binary one state, said method comprising the steps of:
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(a) generating a first binary state of the first and second signals before the first bit of the address signal and after the last bit of the data signal; (b) generating for each bit of the address signal a second binary state of the first signal and the first binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary one state; (c) generating for each bit of the data signal the second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and (d) generating the second binary state of the first and second signals between successive bits of the data signal. - View Dependent Claims (7, 8, 9, 10)
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11. Apparatus for serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said apparatus comprising:
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first means for generating a first binary state of the first and second signals before and after the data signal; second means for generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating a first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and said second means generating the second binary state of the first and second signals between successive bits of the data signal. - View Dependent Claims (12, 13)
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14. Apparatus for receiving a data signal from first and second binary signals serially transmitted by a signal source, the data signal including a plurality of bits each having a binary zero state or a binary one state, the first and second signals having a first binary state before and after the data signal, the first signal having a second binary state and the second signal having a first binary state for data signal bits having a binary zero state, the first signal having a first binary state and the second signal having a binary state for data signal bits having a binary one state, and the first and second signals having a second binary state between successive data signal bits, said receiving apparatus comprising:
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first means responsive to the second binary state of the first and second signals for generating a clock signal; second means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and storing an output signal having a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and third means coupled to the first means and second means for storing the second means output signal in response to the clock signal. - View Dependent Claims (15, 16)
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17. A system for serially communicating data signals, each including a plurality of bits each having a binary zero state or a binary one state, between a transmitting unit and at least one receiving unit intercoupled by first and second binary signals, said system comprising:
a transmitting unit for transmitting a data signal, including; a signal source for providing a data signal; first means for generating a first binary state of the first and second signals before and after the data signal; second means for generating for each bit of the data signal a second binary state of the first signal and a first binary state of the second signal for a bit having a binary zero state, and the first binary state of the first signal and a second binary state of the second signal for a bit having a binary one state; and said second means generating the second binary state of the first and second signals between successive bits of the data signal; and a receiving unit for receiving a data signal transmitted by the transmitting unit, including; third means responsive to the second state of the first and second signals for generating a clock signal; fourth means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and fifth means coupled to the third means and fourth means for storing successive binary states of the fourth means output signal in response to the third means clock signal. - View Dependent Claims (18, 19, 20, 21)
Specification