Synchronizing circuit for use with a telecommunication system
First Claim
1. A synchronizing circuit for use with a digital communication system, said system including a transmission line arranged between a transmitting and a receiving terminal for transmitting a serial data stream at a fixed data rate under control of a system clock pulse train received by a system clock pulse line and arranged in frames each composed of a first data word containing a binary synchronization code for recovering a frame in the continuous serial data stream and a signalling code for enabling control operations of said communication system and at least a second data word containing binary coded information, said synchronizing circuit adapted to be connected to said receiving end of said transmission line for recovering the alignment of consecutive frames in the serial data stream and comprising, in combination:
- (a) a serial/parallel converter being designed for a capacity of one data word of said frame and having a serial data input coupled to said transmission line, a clock input connected to said system clock pulse line, and a plurality of parallel data outputs;
(b) a synchronizing detector logic network having parallel inputs each connected to a respective one of said parallel data outputs of said serial/parallel converter and having a first and a second output, said synchronizing detector logic network generating a first and a second control signal at the respective one of said first and second outputs, wherein a respective one of said control signals occurs whenever a condition at said parallel data outputs of said serial/parallel converter reflects a synchronization code in form of a normal synchronizing bit pattern and an inverted synchronizing bit pattern, respectively;
(c) means for delaying said first control signal for a time period equivalent to the time required for receiving one frame and having an input and an output, said input of said delay means being connected to said first output of said synchronizing detector logic network;
(d) an AND-gate having a first and a second input and an output generating in synchronized operation a synchronizing signal once every alternate frame, said first input of said AND-gate being connected to said output of said delay means and said second input of said AND-gate being connected to said second output of said synchronizing detector logic network; and
(e) a time slot generator having a clock input for receiving said system clock pulse trains, a synchronizing signal input connected to the output of said AND-gate and a first and a second generator output each carrying a respective one of a first and a second enabling signal, said time slot generator including means for counting subsequent clock pulses under control of said synchronizing signal such that during receiving the first data word said first generator output and during the receiving the second data word said second generator output subsequently are carrying a respective one of said enabling signals.
1 Assignment
0 Petitions
Accused Products
Abstract
A synchronizing circuit for use with a digital communication system is disclosed. A serial data stream is arranged in frames composed of at least two data words containing a synchronization signalling code and binary coded information, respectively. For detecting the alignment of consecutive frames the synchronizing circuit includes a serial/parallel converter and a synchronizing detector logic network for generating two control signals indicating the presence of the synchronization code in form of a normal synchronizing bit pattern or an inverted synchronizing bit pattern respectively. An AND-gate logically links the first control signal delayed by one pulse frame to the undelayed second control signal and generates a synchronizing signal. A time slot generator produces enabling signals by means of counting subsequent system clock pulses under control of this synchronizing signal such that during receiving of different data words of a frame a respective one of the enabling signals is present.
23 Citations
9 Claims
-
1. A synchronizing circuit for use with a digital communication system, said system including a transmission line arranged between a transmitting and a receiving terminal for transmitting a serial data stream at a fixed data rate under control of a system clock pulse train received by a system clock pulse line and arranged in frames each composed of a first data word containing a binary synchronization code for recovering a frame in the continuous serial data stream and a signalling code for enabling control operations of said communication system and at least a second data word containing binary coded information, said synchronizing circuit adapted to be connected to said receiving end of said transmission line for recovering the alignment of consecutive frames in the serial data stream and comprising, in combination:
-
(a) a serial/parallel converter being designed for a capacity of one data word of said frame and having a serial data input coupled to said transmission line, a clock input connected to said system clock pulse line, and a plurality of parallel data outputs; (b) a synchronizing detector logic network having parallel inputs each connected to a respective one of said parallel data outputs of said serial/parallel converter and having a first and a second output, said synchronizing detector logic network generating a first and a second control signal at the respective one of said first and second outputs, wherein a respective one of said control signals occurs whenever a condition at said parallel data outputs of said serial/parallel converter reflects a synchronization code in form of a normal synchronizing bit pattern and an inverted synchronizing bit pattern, respectively; (c) means for delaying said first control signal for a time period equivalent to the time required for receiving one frame and having an input and an output, said input of said delay means being connected to said first output of said synchronizing detector logic network; (d) an AND-gate having a first and a second input and an output generating in synchronized operation a synchronizing signal once every alternate frame, said first input of said AND-gate being connected to said output of said delay means and said second input of said AND-gate being connected to said second output of said synchronizing detector logic network; and (e) a time slot generator having a clock input for receiving said system clock pulse trains, a synchronizing signal input connected to the output of said AND-gate and a first and a second generator output each carrying a respective one of a first and a second enabling signal, said time slot generator including means for counting subsequent clock pulses under control of said synchronizing signal such that during receiving the first data word said first generator output and during the receiving the second data word said second generator output subsequently are carrying a respective one of said enabling signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification