Solid-state device

• US 4,371,406 A
• Filed: 01/29/1979
• Issued: 02/01/1983
• Est. Priority Date: 09/28/1965
• Status: Expired due to Term

• Current Assignee: Chou H. Li
• Original Assignee: Chou H. Li
• Inventors: Li, Chou H.
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/007,584
• Time in Patent Office: 1,464 Days
• Field of Search: 148/171, 148/172, 148/173, 148/1.5, 148/33, 148/134 R, 148/134 G, 148/134 S, 75/65 ZM, 29/572, 29/569 L, 357/55, 357/59
• US Class Current: 438/27
• CPC Class Codes: C30B 21/02 by normal casting or gradient freezing
• CPC Class Codes: C30B 21/04 by zone-melting
• CPC Class Codes: H01L 21/24 Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body H01L21/182 takes precedence
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 27/142 Energy conversion devices photovoltaic modules or arrays of single photovoltaic cells comprising bypass diodes integrated or directly associated with the devices H01L31/0443; photovoltaic modules composed of a plurality of thin film solar cells deposited on the same substrate H01L31/046
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 31/00 Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K30/00 takes precedence; devices consisting of a plurality of solid state components formed in, or on, a common substrate, other than combinations of radiation-sensitive components with one or more electric light sources, H01L27/00
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y10S 438/929 : Eutectic semiconductor

Abstract

The ultra-miniaturized, active solid-state devices and circuitries have unique material bodies having signal-translating regions attached thereto for active signal translation. These regions, comprising melt-grown, or simulated melt-grown, metallurgical compounds including oxides, eutectics, and intermetallics, are of controlled compositions, concentration profiles, and electronic or other optoelectromagnetic properties. In some devices, the microstructure of the compounds comprises a plurality of microscopically thin, regularly-shaped and uniformly-spaced bodies of one phase material dispersed in a matrix of another phase material. The electronic conductivity of the bodies is substantially different from that of the matrix, and the bodies all terminate at microscopic distance from the pn junction (or other interfacial rectifying barrier region), so as to confine the signal current carries to flow mainly in only one of the phases. This achieves carriers microstreaming or microbranching effects. Described also herein are different devices including micron-size eutectic devices, dendritic devices, cellular devices, and granular devices; and their methods of manufacture. The barrier regions may be further modified by diffusion, ion implantation, selective oxidation, electrolytic etching, and surface-contouring. In addition, selected circuit elements may be embedded into these devices to achieve additional carriers movement control or to obtain special beneficial effects.

Claims

1. A method of making an active solid-state device comprising:

forming by a process which includes directional melt growth a structure having first phase bodies which are substantially parallel to each other and are spaced from each other by second phase bodies, each of the bodies of at least one of the phases being a single crystal semiconductor substance, the first phase bodies physically contacting the second phase bodies, and the structure including PN junctions which are within the semiconductor material bodies and said structure being crystallographically discontinuous at said physical contact between the first and second phase bodies, and

providing electrical contact to the bodies of at least one of said phases to enable the structure to operate as an active device.

2. A method of making an active solid-state device as in claim 1 in which the forming step includes forming said bodies in an array of first phase bodies of substantially uniform size and shape.

3. A method of making an active solid-state device as in claim 2 including forming, at a side of the array which intersects all of the bodies, a layer of a material which is substantially transparent optically and is electrically conductive, the first phase bodies being of one conductivity type and the layer being of the same conductivity type as, and in electrical contact with, the first phase bodies.

4. A method of making an active solid-state device as in claim 3 in which the second phase bodies are of conductivity type opposite that of the first phase bodies.

5. A method of making an active solid-state device as in claim 2 including recessing the first phase bodies relative to the second phase bodies in a selected direction and introducing optically communicating elements into the so-formed recesses to provide optical communication between said elements and the so-recessed first phase bodies.

6. A method of making an active solid-state device as in claim 5 wherein the first phase bodies are rod-shaped and the optically communicating elements are fiber optics strands having their tips introduced into said recesses.

7. A method of making an active solid-state device as in claim 2 including forming a cut intersecting a multiplicity of adjacent first phase and second phase bodies, said cut separating physically and electrically into two parts each body through which the cut extends.

8. A method of making an active solid-state device as in claim 2 in which the first phase bodies are rod-shaped.

9. A method of making an active solid-state device as in claim 2 in which the first phase bodies are sheets alternating with sheets each of which is a second phase body.

10. A method of making an active solid-state device as in claim 2 in which the first phase bodies are microscopically uniform in size and are microscopically uniformly spaced from each other.

11. A method of making an active solid-state device as in claim 2 in which at least the first phase bodies are a semiconductor material selected from the group consisting of Si, Ge, GaAs, InSb, PbS_1-x Se_x, PbSTe, GaInAs, GaAlAs, GaAsP, PbSnTe, HgCdTe, CdS, GaP and GaAlP.

12. A method as in claim 1 in which said forming step includes subjecting selected starting materials including at least one semiconductor substance and dopants of opposite conductivity types relative thereto to melt growth to thereby form said bodies of the first and second phase and said PN junctions.

13. A method as in claim 1 in which the bodies of both phases are respective semiconductor substances.

14. A method as in claim 1 in which the bodies of the other phase are metal and form a continuous matrix which envelops the semiconductor bodies.

15. A method as in claim 1 in which the bodies of at least one of the phases each have a thickness of from a fraction of a micron to about 15 microns.

16. A method as in claim 1 in which the step of providing electrical contact includes providing respective electrical contacts to the bodies of each phase.

17. A method as in claim 1 in which the forming step comprises providing a melt liquid of a given composition, applying a temperature gradient in the melt along a selected growth direction to produce a directionally grown solidified structure oriented along the direction of the temperature gradient and comprising said first and second phase bodies.

18. A method as in claim 17 in which said growth takes place at a planar growth interface.

19. A method as in claim 17 including adding both N-type and P-type dopants in the melt liquid in quantities sufficient to produce said PN junctions at specified locations within the semiconductor substance bodies of one of said phases.

20. A method of making an active solid-state device comprising:

forming by a process which includes directional melt growth a structure having first phase semiconductor bodies spaced from each other by second phase metal, the semiconductor bodies physically contacting the metal and forming, at said physical contact, respective metal-semiconductor barriers; and

providing electrical contact to at least the metal to enable operation of the structure as an active solid-state device.

21. A method as in claim 20 in which said metal is in the form of a metal matrix and said semiconductor bodies are rod-shaped and are in said matrix.

22. A method as in claim 20 in which both the semiconductor and the metal are in the form of sheet-shaped bodies which alternate with each other.

23. A method as in claim 20 in which the forming step comprises providing a melt liquid of a given composition, applying a temperature gradient to the melt liquid along a selected growth direction to directionally grow a solidified structure oriented along the direction of the temperature gradient and comprising said semiconductor bodies and said metal.

24. A method as in claim 20 in which the metal is a dopant relative to the semiconductor.

25. A method as in claim 20 in which the metal is not a dopant relative to the semiconductor.

26. A method as in claim 20 in which the semiconductor is selected from the group consisting of Si and GaAs.