Stochastic demodulator for phase jump-modulated signals, operating in time divided up over several channels

• US 4,373,151 A
• Filed: 04/08/1980
• Issued: 02/08/1983
• Est. Priority Date: 04/11/1979
• Status: Expired due to Term

• Current Assignee: Le Materiel Telephonique Thomson-Csf
• Original Assignee: Le Materiel Telephonique Thomson-Csf
• Inventors: Houdard, Jean-Pierre, Julie, Jean-Jacques, Leoni, Bernard G.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US06/138,285
• Time in Patent Office: 1,036 Days
• Field of Search: 329/104, 329/105, 375/78, 375/82, 375/83, 375/84, 375/85, 375/86, 375/87
• US Class Current: 329/310
• CPC Class Codes: H04L 27/2338 using sampling H04L27/2331 - H04L27/2335 take precedence

Abstract

The demodulator therefore features a multiplexer connected to the different transmission channels. The output of the multiplexer is connected to a sampler-coder, followed by an interpolator, which is itself followed by a phase jump converter and a statistical decision device validating the code conversion result, when a certain number of samples taken in a series of successive samples have a phase jump in the same range of values.

Claims

1. A demodulation process for phase jump-modulated signals, in particular for the processing in time divided up over a plurality of transmission channels, comprising the steps of:

sampling and coding said signals on reception;

interpolating said sampled and coded signals in such a way as to obtain a whole number n of samples for each information symbol;

comparing with a fixed reference signal the phase deviation of each sample obtained after interpolation is calculated, wherein the thus calculated phase deviation of each sample is compared with the phase deviation calculated in the same way for the sample preceding the sample under consideration by n units;

code converting the result of the said comparison by comparing with a phase jump value having different comparison results, but which are in a same range of values;

starting a counter when the results of said comparison cross a threshold with said threshold corresponding to a given number of samples taken from a series of successive samples and all belonging to the same range of values; and

validating the result of said comparison when said counter reaches a given state to thereby output a demodulated signal.

2. A process according to claim 1, wherein the counter is reset whenever the crossing of a threshold has been determined for a range of values differing from that for which the count is taking place.

3. A process according to claim 1 or 2, wherein the sampled and coded signal received is interpolated in such a way that the new sampling frequency resulting from the interpolation is the smallest common multiple of the sampling frequency before interpolation and the modulating frequency on transmission.

4. A process according to claims 1 or 2, wherein the sampled and coded signal received is interpolated in such a way that the new sampling frequency resulting from the interpolation is a whole multiple, advantageously three times the sampling frequency before interpolation, the latter being a whole multiple of the modulating frequency.

5. A process according to claim 1, wherein said reference signal is generated by directly producing in digital form reference phase values at a frequency equal to that of a carrier of the said transmitted data.

9. A process according to claim 1 or 2 wherein the result of said code conversion is in the form of dibits.

10. A process according to claim 1 or 2 wherein the result of said code conversion is in the form of tribits.

6. A demodulator for processing phase jump-modulation intended to operate in time divided up over a plurality of channels comprising;

a multiplexer, a sampler-coder connected to the output of said multiplexer, an interpolator connected to the output of said sampler-coder, a phase jump computer for receiving the output of said interpolator and a statistical decision device connected to the output of said computer.

7. A demodulator according to claim 6, wherein the phase jump computer comprises a calculating circuit with a non-recursive digital network and a divider for calculating the tangent of the argument of each incident signal, said calculating circuit being connected to a first read-only code conversion memory, whose output is connected to a first input of a first adder, whose second input is connected to the output of a second read-only memory controlled by an addressing counter and in which are stored reference phase values at the frequency of the carrier of the incident analog signals, the output of the first adder being connected both to a first input of a second adder and to a digital delay line incorporating a number of elements equal to the number of samples of a symbol, the output of said delay line being connected to the second input of the second adder.

8. A demodulator according to either of the claims 6 and 7, wherein the statistical decision device comprises a coding read-only memory on each of the different outputs of which appears a 1 when the phase determined by the calculating circuit is in the corresponding range of the phase deviations, each of its outputs being connected on the one hand to a read-only memory for code conversion into dibits or tribits and on the other hand to a digital delay line incorporating a number of elements which preferably exceeds 2 to 3 units at the value of said threshold, the different outputs of the elements of this delay line being connected to the different inputs of a presence probability read-only memory realised in such a way that a 1 is produced at its output when the number of elements of the corresponding digital delay line having the 1 is at least equal to the said threshold, the output of the different read-only memories being on each occasion connected on the one hand to a first series of corresponding inputs to a comparator via a first bistable multivibrator register and on the other hand to a second series of inputs of said comparators via a second bistable multivibrator register, the output of said comparator being connected on the one hand, via a logic inverter, to the timing signals input of a first bistable multivibrator which is connected to the output of the said read-only code conversion memory and on the other hand to the resetting input of a counter, whose different outputs are connected to a decoder, the output of said decoder being connected to the timing signals input of a second bistable multivibrator connected to the output of the first bistable multivibrator, the outputs of second bistable multivibrator constituting the outputs of the demodulator.