Very high density punch-through read-only-memory

• US 4,373,165 A
• Filed: 09/14/1981
• Issued: 02/08/1983
• Est. Priority Date: 11/07/1979
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tasch, Al F. Jr.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US06/301,504
• Time in Patent Office: 512 Days
• Field of Search: 357/13, 357/45, 365/105, 365/175
• US Class Current: 257/497
• CPC Class Codes: H10B 20/10 ROM devices comprising bipolar components
• CPC Class Codes: Y10S 257/926 Elongated lead extending axially through another elongated lead

Abstract

A semiconductor read-only-memory (ROM) device having an array of punch-through devices as memory cells. The cells are formed at the crossing points of two pluralities of parallel elongated regions, the two pluralities being perpendicular to each other. One plurality is located in subsurface regions of a semiconductor body and is of a conductivity type opposite that of the surrounding body. The other plurality is located at a surface of the semiconductor body and is of the same conductivity type as the subsurface plurality. The device is programmed by implanting impurities of the same conductivity type as the semiconductor body between selected crossing points. No contacts exists in the array.

Claims

1. A semiconductor device comprising:

a body of monocrystalline semiconductor of one conductivity type having a plurality of parallel, elongated, surface regions of opposite conductivity type;

a plurality of elongated, subsurface parallel regions of opposite conductivity type, perpendicular to said surface plurality and spaced therefrom to form a criss-cross pattern; and

a subsurface plurality of regions of said one conductivity type located between selected crossing points of said pattern, said respective subsurface regions each being more heavily doped than said body of monocrystalline semiconductor.

2. A semiconductor device according to claim 1 further including an insulating layer upon said device.

3. A semiconductor device according to claim 1 wherein said body and said subsurface plurality are p-type and said surface and subsurface parallel pluralities are n-type.

4. A semiconductor device according to claim 1 further including metal silicide regions in said surface parallel plurality.

5. A semiconductor device according to claim 4 further including an insulating layer upon said device.

6. A semiconductor device according to claim 4 wherein said body and said subsurface plurality are p-type and said surface and subsurface parallel pluralities are n-type.

7. A semiconductor device according to claim 4 wherein said metal silicide regions are platinum silicide.