Signal conversion device

• US 4,373,189 A
• Filed: 08/28/1980
• Issued: 02/08/1983
• Est. Priority Date: 08/28/1980
• Status: Expired due to Term

• Current Assignee: Charles M. Weant
• Original Assignee: Charles M. Weant
• Inventors: Weant, Charles M.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US06/182,290
• Time in Patent Office: 894 Days
• Field of Search: 364/600, 364/602, 364/607, 364/608, 340/347 SY, 340/347 AD, 328/14, 328/21-25
• US Class Current: 708/3
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06

Abstract

A solid-state, signal conversion circuit for converting electrical, periodic analog signals to other analog signals of different amplitude and/or frequency and/or phase is disclosed. The input signal is demodulated, scaled and sampled and each sample converted, via an analog-to-digital (A/D) converter, to a digital word corresponding to the sample'"'"'s amplitude. The digital words address a ROM which has other words stored at the addresses in correspondence with the desired values for a preselected output signal. Scaling means is used to keep the input signal to the A/D converter at a constant peak value regardless of fluctuations in the signal level. A comparator and subtractor are used to invert the downslope of input signals to avoid ambiguity problems when the output signal frequency is an even multiple of the input signal frequency.

Claims

1. A signal conversion circuit for converting a periodic, analog, electrical input signal into an output signal differing from the input signal in amplitude and/or frequency and/or phase comprising:

scaling means for changing the amplitude of the input signal so that the peak thereof equals a preselected value;

A/D converter means operatively connected to said scaling means for sampling the amplitude of the input signal and changing the sampled values to an equivalent set of digital words, each digital word corresponding to the value of its associated sample;

a comparison, subtraction and scale adjustment (CSSA) means operatively connected to said A/D converter means and to said scaling means for receiving the output of said A/D converter means and storing it until the next output thereof is received, and for comparing each present output sample (t_n) of said A/D converter means with its prior output sample (t_n-1) once each cycle of the input signal V_i of said signal conversion circuit, the present and prior output samples being used to correct the scaling of said scaling means;

ROM means operatively connected to said CSSA means so as to receive the output of said A/D converter means, in the form of output digital words, for storing at each digital word address thereof another digital word in accordance with pre-programmed values corresponding to the values of a desired output signal; and

D/A converter means operatively connected to said ROM means for converting the output digital words thereof into corresponding analog values.

2. The signal conversion circuit of claim 1 further comprising, smoothing means operatively connected to said D/A converter means for converting the analog values therefrom into corresponding smooth continuous waveforms.

3. The signal conversion circuit of claim 2 further comprising:

means for receiving a modulated input signal and removing the carrier frequency thereof so as to feed the envelope of the modulated input signal to said scaling means; and

means for receiving the output of said smoothing means as an input signal and using it to modulate a carrier frequency to provide a modulated carrier signal as the output of said signal conversion circuit.

4. The signal conversion circuit of claims 3 or 1 in which said CSSA means further comprises:

a first latch for receiving the output of said A/D converter means and storing it until the next A/D output signal is received, the signal at the input of said first latch being the present (t_n) output sample of said A/D conversion means and the signal at the output of said first latch being the prior (t_n-1) output sample;

a comparator for comparing each t_n sample with each prior t_n-1 sample and providing a first output signal which is high only when t_n >

t_n-1 and a second output signal which is high only when t_n <

t_n-1 ;

first AND gates for receiving the output of said first latch and the first output signal from said comparator for passing through to said ROM means the output of said first latch when the first output signal from said comparator is high (t_n >

t_n-1);

a second latch including a latch circuit portion and a one-shot multivibrator (MV) portion, said latch circuit portion receiving the t_n-1 sample at its input and said MV portion receving the second output signal from said comparator at its input, said MV portion operating on the leading edge of the second output signal to activate the operation of said latch circuit portion so that the signal at the output thereof is always the peak value of the input signal V_i for a single cycle thereof;

subtraction means for receiving as a first input the peak value of the input signal V_i from the output of said latch circuit portion of said second latch, as a second input the t_n-1 sample from said first latch and as an enabling signal the second output signal from said comparator, and operating to substract the t_n-1 sample from the peak value of the input signal V_i to obtain a difference signal when the second output signal from said comparator is high (t_n <

t_n-1) and for passing on the difference signal to said ROM means only when t_n <

t_n-1 ;

second AND gates for receiving the output of said substraction means as a first input and the second output signal from said comparator as a second input; and

OR gates having inputs connected to the outputs of said first and second AND gates and having outputs connected to input lines of said ROM means.