Digital frequency and phase lock loop

• US 4,374,438 A
• Filed: 07/21/1980
• Issued: 02/15/1983
• Est. Priority Date: 07/21/1980
• Status: Expired due to Term

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: RCA Corporation
• Inventors: Crowley, Albert T.
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US06/170,999
• Time in Patent Office: 939 Days
• Field of Search: 455/260, 455/265, 455/208, 331/1 A, 331/17, 331/18, 331/25, 375/119, 375/120, 329/122, 329/123, 324/83 A, 324/83 D, 324/83 FE, 328/133, 328/155, 343/6.8 LC, 343/7 PL
• US Class Current: 455/265
• CPC Class Codes: G01S 13/82 wherein continuous-type signals are transmitted
• CPC Class Codes: H03L 7/0994 comprising an accumulator

Abstract

An improved jitter-free system for phase locking a locally generated signal with a received signal. The system provides and arithmetic synthesizer having a clock signal source which clocks a binary increment contained in an input register into the digital accumulator of the arithmetic synthesizer. A converter converts the output of the accumulator into the locally generated two-level signal whose frequency is determined by the average overflow rate of the accumulator. Logic including a phase detector compares the phases of the received and locally generated signals to produce an error signal whose magnitude is proportional to the phase difference between the received and locally generated signals and also an early/late phase changing periodic two level signal. A voltage-to-frequency (V/F) converter responds to said error signal to produce a first signal whose frequency is proportional to the magnitude of the error signal. An up/down counter means responds to the first signal to count at a rate equal to the frequency thereof and in a direction determined by the level of the periodic two level signal. The input register responds to the count in said up/down counter to vary the binary increment supplied to the accumulator to phase lock the received and locally generated signals.

Claims

1. In a communication system including phase locked loop means for phase locking a locally generated signal with a cyclical portion of a received signal and comprising:

signal value producing means comprising an accumulator, an input register containing a variable value and means including a clock signal source for enabling supply of said variable value to said accumulator at the frequency of said clock signal, with said accumulator being responsive to said variable value being supplied thereto to produce a series of output values representative of a frequency of said locally generated signal;

signal processing means responsive to said series of output values to produce said locally generated signal;

logic means responsive to said locally generated signal and said cyclical portion of said receiver signal to produce an error voltage indicative of the phase difference therebetween and to produce a periodic two level signal;

voltage to frequency converting means for converting said error voltage into a count control signal whose frequency is proportional to said error voltage;

up/down counter means responsive to said count control signal and to said two level periodic signal to count at a rate equal to the frequency of said control signal and in a direction determined by said two level periodic signal to provide a variable output count value; and

means responsive to said periodic two level signal for altering the variable value contained in said input register to correspond to said variable output, count value of said up/down counter means.

2. A communication system as in claim 1 in which said received signal further comprises an encoded portion preceding said cyclical portion, and further comprising:

correlating means responsive to said encoded portion of received signal to produce a correlation signal;

said phase locked loop means being responsive to said correlation signal to become energized to lock the phase of said locally generated signal with the cyclical portion of said received signal; and

means responsive to the phase locked condition of said received cyclical signal portion and said locally generated signal to generate and transmit a signal having an encoded portion and a second cyclical portion whose phases are identical, respectively, with the phases of the encoded and cyclical portions of the received signal.

3. A communication system as in claim 1 in which said logic means further comprises:

means responsive to said periodic signal to alternately retard and advance the phase of said locally generated signal during phase lacking thereof with said cyclical portion of said received signal.

4. A communication system as in claim 1 and further comprising a phase error lead means responsive to the output of said accumulator and the count in said up/down counter means to alter the phase of the signal-representing output values supplied from said accumulator by an amount determined by the then currently indicated phase difference between the locally generated signal and said cyclical portion.

5. A communication system as in claim 4 in which said phase error lead means is responsive to said periodic two level signal to produce alternate retarding and advancing of the phase of said locally generated signal.