Self-calibrating overcurrent detector

• US 4,375,072 A
• Filed: 03/30/1981
• Issued: 02/22/1983
• Est. Priority Date: 04/10/1980
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rice, Anthony J.
• Primary Examiner(s): EISENZOPF, REINHARD
• Application Number:
  US06/248,742
• Time in Patent Office: 694 Days
• Field of Search: 361/87, 361/93, 361/31, 324/130, 324/51, 340/664, 364/571, 364/483, 364/580
• US Class Current: 361/87
• CPC Class Codes: G01R 19/16571 comparing AC or DC current with one threshold, e.g. load current, over-current, surge current or fault current G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533, G01R19/1659 take precedence; measuring currents by using elements sensitive to the magnetic field generated G01R15/14; measuring earth resistance G01R27/18; testing for leakage or short circuits in electrical apparatus G01R31/52
• CPC Class Codes: H02H 3/006 Calibration or setting of parameters
• CPC Class Codes: H02H 3/08 responsive to excess current responsive to abnormal temperature caused by excess current H02H5/04

Abstract

Circuit for detecting a fault current in an installation where the load (RL) varies. Total current (IS) is converted into a voltage (VS). During an initialization cycle, means such as counter (9), digital-to-analog converter (10), comparator (5), resistors (R1, R2) generate a voltage (VS) equal to VS at the end of the initialization cycle, and a threshold voltage VS=kVS. During operation, voltage VS is compared with threshold VD in order to provide a fault detection indication which is transmitted to the protection circuit by a logic circuit, that is, AND gate (17) and OR gate (19). During the initialization cycle, protection is obtained by comparing VS with a reference voltage in a comparator (7). This device is used to protect machines having an expandable configuration.

Claims

1. Self-calibrating overcurrent detector characterized in that it includes:

means for generating a first voltage (VS) which is proportional to the current whose fault value is to be detected,

means which are active during an initialization cycle for generating a second increasing voltage (VC) which, at the end of the initialization cycle, is equal to the first voltage and for deriving from said second voltage a threshold voltage (VD) such that VS=kVC, k being a numerical factor higher than 1, and

first means for comparing the threshold voltage with the first voltage in order to provide a fault detection indication after the initialization cycle.

2. Circuit according to claim 1 characterized in that it includes second comparison means for comparing the first voltage to a reference voltage in order to provide a fault detection indication during the initialization cycle.

3. Circuit according to claim 1 or 2 characterized in that it includes means to prevent the first comparison means from generating the fault detection indication during the initialization cycle.

4. Circuit according to claim 3 characterized in that the means for generating the second voltage (VC) include:

a counter provided with a counting input and a resetting input,

means for applying to the counting input of the counter clock pulses during the initialization cycle,

means for generating a count control signal,

analog-to-digital converter whose input receives the output signals of the counter and which provides the threshold voltage.

5. Circuit according to claims 1 or 2 characterized in that the means for generating the second voltage (VC) include:

a counter provided with a counting input and a resetting input,

means for applying to the counting input of the counter clock pulses during the initialization cycle,

means for generating a count control signal,

analog-to-digital converter whose input receives the output signals of the counter and which provides the threshold voltage.

6. Circuit according to claim 5 characterized in that the means for generating the second voltage (VC) comprise two resistors mounted in series between the converter output and a second reference voltage, voltage VC being drawn at the common resistor point.

7. Circuit according to claim 6 characterized in that the means for generating the count control signal include third comparison means which compare the first voltage with the second voltage (VC) and provides the count control signal if said second voltage is lower than the first one.

8. Circuit according to claim 7 characterized in that it comprises an AND gate having three inputs, the first input receiving a signal which activates the gate during the initialization cycle and deactivates it during operation time, the second input receiving the clock signal, and the third input receiving the count control signal, and one output connected to the counter input.

9. Circuit according to claim 8 characterized in that the means for preventing the generation of the fault indication during the initialization cycle include a second AND gate having two inputs, the first one receiving a signal to deactivate the gate during the initialization cycle and to activate it during machine operation, the second input being connected to the output of the first comparison means, the output of said gate providing the fault detection indication during the initialization cycle.

10. Circuit according to claim 9 characterized in that it comprises an OR gate having two inputs, the first one receiving the fault detection indication provided by the second comparison means, the second one receiving the indication provided by the second AND gate and whose output generates a control signal to stop the power supply.