Volatile/non-volatile dynamic RAM system

• US 4,375,086 A
• Filed: 05/15/1980
• Issued: 02/22/1983
• Est. Priority Date: 05/15/1980
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: van Velthoven, Armand J.
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US06/150,275
• Time in Patent Office: 1,013 Days
• Field of Search: 365/185, 365/184, 365/149, 365/228
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A volatile/non-volatile dynamic RAM cell and system in which the cell comprises a storage capacitor for volatilely storing binary information during normal RAM operation; an alterable-threshold storage capacitor for non-volatilely storing the information in non-volatile fashion during power off conditions; and an energy barrier between the two capacitors. Information can be restored to the volatile capacitor either by CCD charge transfer or by charge-pumped operation. The energy barrier facilitates efficient charge pumped restore of information. In one embodiment, the energy barrier is a high concentration substrate surface region having the same conductivity type as the substrate. Alternatively, the alterable-threshold non-volatile capacitor and the energy barrier are provided by a split-gate capacitor which has an alterable threshold non-volatile section (the non-volatile capacitor) and a non-alterable threshold section (the energy barrier).

Claims

1. A volatile/non-volatile RAM cell having volatile data store, volatile-to-nonvolatile store, and nonvolatile-to-volatile restore capabilities, comprising:

volatile storage means, including a capacitor, for storing binary charge data;

non-volatile storage means for selectively storing the charge data in the volatile storage means;

means for providing a preselected energy barrier which must be overcome for charge transfer between the volatile storage means and the non-volatile storage means; and

a charge transfer device for effecting the charge storage state of the volatile storage means during volatile operation and in cooperation with the nonvolatile storage means effecting the nonvolatile-to-volatile restore operation.

2. The volatile/non-volatile RAM cell of claim 1 wherein the non-volatile storage means and the barrier means comprise, respectively, a non-volatile alterable-threshold section and a non-alterable threshold section of a split gate capacitor.

3. The volatile/non-volatile RAM cell of claim 2 wherein the split gate capacitor is MNOS or SNOS.

4. A volatile/non-volatile dynamic field-effect RAM cell having volatile data store, volatile-to-nonvolatile store, and nonvolatile-to-volatile restore capabilities, comprising:

a semiconductor substrate of a first conductivity type;

a capacitor formed in said substrate for storing binary information in the form of charge volatilely stored therein;

means for selectively supplying charge to said volatile capacitor;

a nonvolatile capacitor formed in said substrate operable for selectively receiving, storing and restoring to the volatile capacitor the binary charge information;

energy barrier means in said substrate interposed between said volatile capacitor and said nonvolatile capacitor, said energy barrier means providing a predetermined energy barrier to charge transfer from said nonvolatile capacitor to said volatile capacitor; and

wherein said means for supplying charge includes a charge transfer device for effecting the charge storage state of the volatile storage capacitor during volatile operation and cooperating with the nonvolatile capacitor to effect the nonvolatile-to-volatile restore operation.

5. The volatile/nonvolatile dynamic field-effect RAM cell of claim 4, said energy barrier means comprising a substrate impurity region of the first conductivity type.

6. The volatile/nonvolatile dynamic field-effect RAM cell of claim 4, said energy barrier means and said nonvolatile capacitor comprising a split-gate capacitor of the type CI₁ I₂ S, wherein C is a gate electrode, I₁ is a dielectric such as silicon nitride, I₂ is a dielectric such as silicon dioxide, and S is said semiconductor substrate;

said energy barrier means comprising a non-alterable threshold section of said split gate capacitor; and

said nonvolatile capacitor comprising an alterable threshold, nonvolatile section of said split gate capacitor.

7. In a volatile/nonvolatile dynamic field-effect RAM cell comprising a semiconductor substrate, a capacitor formed in the substrate for volatilely storing binary charge information, means for selectively supplying charge to the volatile capacitor, and nonvolatile capacitive charge storage means, the improvement comprising structure suitable for effecting charge pumped restore or charge transfer restore to the volatile capacitor of information stored in said nonvolatile charge storage means, characterized by said nonvolatile charge storage means comprising a split gate capacitor having an alterable threshold, nonvolatile section and a non-alterable threshold section interposed between said nonvolatile section and said volatile capacitor, said non-alterable capacitor section providing a substrate surface potential barrier for preventing charge leakage from said volatile capacitor to said non-volatile section during the charge pumped restore operation.

8. The volatile/nonvolatile RAM cell of claim 7 wherein said split gate capacitor is selected from one of CI₁ I₂ S and CI₁ I₂ I₃ S, wherein C is a conductive gate electrode;

I₁, I₂ and I₁, I₂, I₃ are multiple layer gate insulators; and

S is said semiconductor substrate.

9. A volatile/non-volatile dynamic random access memory system having volatile store, volatile-to-nonvolatile store, and nonvolatile-to-volatile restore capabilities, comprising:

a plurality of volatile/non-volatile dynamic field effect memory cells formed in a substrate;

each cell comprising a capacitor formed in the substrate for volatilely storing binary charge information;

non-volatile capacitive charge storage means suitable for effecting charge-pumped restore or charge transfer restore to the volatile capacitor of information stored in said non-volatile charge storage means;

a transfer gate for controlling the application of binary charge information to the volatile capacitor for volatile storage and to the non-volatile storage means to initiate nonvolatile-to-volatile restore to the volatile capacitor;

said non-volatile storage means comprising a split gate capacitor section having an alterable threshold, non-volatile section and a non-alterable threshold capacitor section interposed between said non-volatile section and said volatile capacitor;

said non-alterable capacitor section providing a substrate surface potential barrier for preventing charge leakage from said non-volatile capacitor section to said volatile capacitor during charge-pumped restore operation;

amplifier means including an output terminal, said amplifier means being connected to said memory cells and being responsive to a voltage stored on said volatile capacitor representing the binary state of said capacitor for generating a signal representing said voltage at said output node; and

means for accessing the signal information at said output node.

10. The random access memory system of claim 9, further comprising:

said amplifier means being a bistable multivibrator including a pair of nodes;

said plurality of memory cells comprising two arrays, the first array being connected to one of said nodes, and the second array being connected to the second of said nodes for controlling the binary state of said multivibrator; and

said accessing means being connected to one of said nodes.