Transistor circuit having two comparator levels

• US 4,375,598 A
• Filed: 04/03/1980
• Issued: 03/01/1983
• Est. Priority Date: 04/05/1979
• Status: Expired due to Term

• Current Assignee: TOKO Incorporated (Murata Manufacturing Co Limited)
• Original Assignee: TOKO Incorporated (Murata Manufacturing Co Limited)
• Inventors: Sakai, Koichi
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/136,752
• Time in Patent Office: 1,062 Days
• Field of Search: 307/290, 307/358, 307/359, 307/360, 307/601, 307/608, 307/299 B
• US Class Current: 327/72
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/2897 with an input circuit of differential configuration

Abstract

A comparator receives an input voltage as well as one of two comparator levels and compares them to selectively produce one of two outputs having different values. A comparator level generator is connected to the comparator for selectively applying one of the two comparator levels to the comparator under the control of a controlling means. The controlling means is connected to both of the comparator level generator and the comparator for controlling the comparator level generator so as to change the comparator level in response to the new state of the comparator.

Claims

1. A transistor circuit having two different comparator reference levels to establish stable hysteresis comprising:

an input terminal;

an output terminal;

a comparator reference level applied terminal;

a constant current source;

first and second transistors having emitters connected respectively to said constant current source and having bases connected respectively to said input terminal and said comparator reference level applied terminal;

a comparator reference level generator including a plurality of resistors arranged in series, and being connected to said comparator reference level applied terminal for selectively generating and applying to said applied terminal one of said two comparator reference levels;

a third transistor the collector and the emitter of which are connected across one of the resistors of said comparator reference level generator;

a current mirror circuit including a fourth transistor and a multi-collector transistor, the base of said fourth transistor being connected to both the collector of said fourth transistor and the collector of said first transistor, and the emitter of said fourth transistor being connected to a power supply, said multi-collector having first, second and third collectors, the base of said multi-collector transistor being connected to the base of said fourth transistor, said first collector being connected to the collector of said second transistor, said second collector being connected to the base of said third transistor, said third collector being connected to said output terminal, and the emitter of said multi-collector transistor being connected to the power supply.

2. A transistor circuit having two different comparator references levels to establish stable hysteresis comprising:

an input terminal;

an output terminal;

a comparator reference level applied terminal;

a constant current source;

first and second transistors having emitters connected respectively to said constant current source and bases connected respectively to said input terminal and said comparator reference level applied terminal;

a comparator level generator including a plurality of resistors arranged in series, and being connected to said comparator reference level applied terminal for selectively generating and applying to said applied terminal one of said two comparator reference levels;

a third transistor the collector and the emitter of which are connected across one of the resistors of said comparator reference level generator;

a current mirror circuit including a multi-collector transistor having first, second third and fourth collectors, the base of said multi-collector transistor being connected to both said first collector and the collector of said first transistor, said second collector being connected to the collector of said second transistor, said third collector being connected to the base of said third transistor and said fourth collector being connected to said output terminal, and the emitter of said multi-collector transistor being connected to a power supply.