Memory system employing mostly good memories

• US 4,376,300 A
• Filed: 01/02/1981
• Issued: 03/08/1983
• Est. Priority Date: 01/02/1981
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tsang, Siu K.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/221,316
• Time in Patent Office: 795 Days
• Field of Search: 365/189, 365/200, 365/210, 371/10, 371/11, 371/21
• US Class Current: 365/200
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A memory system is described which employs a plurality of "mostly good" memory chips. A redundant memory chip is used to store data designated to the defective locations in the mostly good memories. In one embodiment a PROM is programmed to recognize the addresses of the defective elements and to cause the redundant memory to be selected. In another embodiment, a content-addressable memory is employed to provide a new address in response to the addresses of defective elements in the mostly good memories.

Claims

1. In a memory system employing a plurality of memories, each of which are coupled to receive first and second address signals for accessing first and second lines, respectively in said memories, an improvement for permitting use of ones of said memories having defective elements, comprising:

a plurality of said memories, each having defective first lines which are accessed by different first address signals, said memories coupled to receive said first and second address signals;

a programmable memory, programmed to provide a predetermined output signal upon receipt of each of said different first address signals, said programmable memory coupled to receive said first address signals;

an additional memory, coupled to receive said first address signals; and

,

a selection means for selecting signals such that said additional memory is selected when said defective first lines are accessed, said selection means coupled to said memories and said additional memory, said selection means being controlled by said predetermined output signal from said programmable memory so as to cause selection of said additional memory,

whereby a plurality of mostly good memories may be used in said memory system for said memories.

2. The memory system defined by claim 1 including additional address signals which are coupled to said memory system for selecting between ones of said memories, said additional address signal and said second address signals identifying one of said lines in said memories, said additional address signals being coupled to said programmable memory.

3. The memory system defined by claim 2 wherein said programmable memory is a programmable read-only memory.

4. The memory system defined by claim 2 wherein said programmable memory is a content-addressable memory.

5. The memory system defined by claim 1 wherein said selection means selects among said memories by controlling an address timing signal.

6. The memory system defined by claim 1 wherein said selection means is a switching means coupled to the data lines of said memories.

7. In a memory system which includes a plurality of memories which are coupled to receive address signals for accessing said memories, an improvement which permits use of ones of said memories having defective elements comprising:

a memory means coupled to receive said address signals for providing predetermined address signals and a control signal in response to ones of said address signals corresponding to said defective elements of said memories;

an additional memory coupled to receive said predetermined address signals from said memory means; and

,

selection means for selecting either said memories or said additional memory, said selection means controlled by said control signal, so as to select said additional memory for said ones of said address signals corresponding to said defective elements of said memories;

whereby mostly good memories may be used in said memory system for said memories.

8. The memory system defined by claim 7 wherein said memory means comprises a content-addressable memory.

9. The memory system defined by claim 8 wherein said memory means is programmable.

10. The memory system defined by claim 7 wherein said memory system receives additional address signals for selecting between ones of said memories, said additional address signals being coupled to said memory means.

11. The memory system defined by claim 7 wherein each of said memories is disposed on separate substrates and wherein each substrate includes redundant elements.

12. The memory system defined by claim 7 wherein said selection means selects among said memories by controlling an address timing signal.

13. The memory system defined by claim 7 wherein said selection means is a switching means coupled to the data lines of said memories.