Data distribution interface

• US 4,377,843 A
• Filed: 04/19/1979
• Issued: 03/22/1983
• Est. Priority Date: 04/19/1979
• Status: Expired due to Term

• Current Assignee: Wescom Switching Incorporated
• Original Assignee: Wescom Switching Incorporated
• Inventors: Gierut, Lacrence G., Garringer, Roy T.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US06/031,374
• Time in Patent Office: 1,433 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/77, 370/112
• US Class Current: 710/71
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

A microprocessor-based circuit for interfacing between a plurality of serial data terminals and an external parallel data operating system. The interface circuit includes an asynchronous receiver-transmitter, which converts serial data to parallel data and converts parallel data to serial data. The interface circuit multiplexes received serial data from the terminals and couples that serial data to the receiver-transmitter. The microprocessor in the interface circuit further controls the transfer of this now-parallel data to the external parallel data operating system. The microprocessor also controls the transfer of parallel data from the parallel data operating system, which is converted to serial data by the asynchronous receiver-transmitter, demultiplexed by the interface circuit and transmitted to the terminals. Both the transmission and the reception of serial data is coordinated by the microprocessor, which also controls the receiver-transmitter and a set of registers connected to the operating system on a parallel data bus.

Claims

1. A data distribution interface between a plurality of remote serial data terminals and a central parallel data transmission system comprising:

an asynchronous receiver transmitter operable to convert serial data at a serial data input to parallel data at a parallel data output and also operable to convert parallel data at a parallel data input to serial data at a serial data output;

a parallel data bus connected to the parallel data input and output of the asynchronous receiver-transmitter for transmitting parallel data to and from said receiver-transmitter,

multiplexer means coupled to the serial data input of the asynchronous receiver-transmitter and to the plurality of remote serial data terminals for coupling data from said terminals to the serial data input of the asynchronous receiver-transmitter;

demultiplexer means coupled to the serial data output of the asynchronous receiver-transmitter and to the plurality of remote serial data terminals for coupling data from the serial data output of the asynchronous receiver-transmitter to said terminals;

a memory coupled to said parallel data bus

microprocessor means connected to said receiver-transmitter and said data bus for reading and processing data from the data bus and sending resultant data to the memory, for supplying said multiplexer and demultiplexer means with data representing the addresses of selected remote terminals to which data is to be transmitted and from which data is to be received, and for enabling said receiver-transmitter to supply data to said demultiplexer via said serial data output and to receive data from said multiplexer via said serial data input.

2. The data distribution interface of claim 1 wherein said microprocessor means is connected to said memory and includes means for enabling said memory and said receiver-transmitter to supply said receiver-transmitter with data from selected locations in said memory via said parallel data bus, and to supply selected locations in said memory with data from said receiver-transmitter via said parallel data bus.

3. The data distribution interface of claim 1 which further comprises an asynchronous parallel data transfer latch circuit interposed between the parallel data transmission system and the parallel data bus for temporarily storing data being transmitted between said parallel data transmission system and said parallel data bus.

4. The data distribution interface of claim 1 which includes means for generating a clocking signal, and a latch circuit connected between said data bus and said multiplexer means for supplying said address data to said multiplexer means in response to said clocking signal.

5. The data distribution interface of claim 1 in which the multiplexer means comprises an encoder coupled to the data bus and a tri-state receiver circuit connected between said encoder and said remote terminals for transferring data from a plurality of tri-state data line pairs from the terminals to single data lines which are coupled to the encoder.

6. The data distribution interface of claim 1 in which the demultiplexer means comprises a first decoder receiving serial data from the serial data output of the asynchronous receiver-transmitter, and a second decoder, each of said decoders receiving parallel address data from said receiver-transmitter via said data bus and having a plurality of serial data output lines, and a tri-state driver circuit having a plurality of tri-state driver devices each associated with a remote serial data terminal and connected to the plurality of serial data output lines from the first decoder for transmitting the data on those lines to a plurality of tri-state data line pairs, the first decoder being responsive to said address data to couple incoming serial data from the asynchronous receiver-transmitter to a selected one of the serial data output lines from said first decoder, and the second decoder being responsive to the same address data to select the appropriate tristate driver device in the driver circuit to transmit the serial data from said first decoder on the appropriate data line pair to a terminal.

7. The data distribution interface of claim 1 in which the memory comprises both a read only memory and a random access memory.

8. The data distribution interface of claim 3 in which the parallel data transfer latch circuit comprises a first-in first-out latch for data flow in both directions between the parallel data transmission system and the parallel data bus.

9. The data distribution interface of claim 8 which further comprises a grab/release circuit connected to the first-in first-out latch circuit, the external data operating system and the data bus, the grab/release circuit being responsive to the reading and writing of data for each direction of data flow through the first-in first-out latch circuit to prevent simultaneous reading and writing of data in the same direction.

10. The data distribution interface of claim 1 in which the asynchronous receiver-transmitter is a Universal Asynchronous Receiver-Transmitter.

11. A data distribution interface circuit positioned between a plurality of serial data terminals and a central parallel data transmission system comprising:

converting means for converting serial data at a serial data input to parallel data at a parallel data output and for converting parallel data at a parallel data input to serial data at a serial data output;

a parallel data bus connected to the parallel data input and output of the converting means for transmitting parallel data to and from said converting means;

multiplexer means coupled to the serial data input of said converting means and to the plurality of serial data terminals for coupling data from a selected terminal to the serial data input of the converting means;

demultiplexer means coupled to the serial data output of said converting means and to the plurality of serial data terminals for coupling data from the serial data output of the converting means to a selected terminal;

a memory coupled to said parallel data bus

microprocessor means connected to said data bus for reading and processing data from the data bus and sending resultant data to the memory, and for supplying said multiplexer and demultiplexer means with data representing the addresses of selected remote terminals to which data is to be transmitted and from which data is to be received;

means for enabling said multiplexer means to transmit data from said converting means to said selected remote terminals; and

means for enabling said demultiplexer means to transmit data to said converting means from said selected remote terminals.

12. The interface circuit of claim 11 in which said microprocessor means synchronously selects the remote terminals to which serial data is to be transmitted and from which serial data is to be received.

13. The interface circuit of claim 12 in which said converting means produces interrupt signals in response to completion of successive data transmissions to said remote terminals, and said microprocessor means synchronously advances its terminal selections in sequential interrupt periods established by the reception of said interrupt signals from the converting means.

14. The interface circuit of claim 11 in which the converting means, multiplexer means, and demultiplexer means include means for simultaneously coupling data from a selected terminal to the serial data input of the converting means and from the serial data output of the converting means to a selected terminal.

15. The interface circuit of claim 11 which further comprises a clock utilized by the converting means.

16. The interface circuit of claim 15 in which the converting means is an asynchronous receiver-transmitter.