Register allocation apparatus
First Claim
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1. For use in a data processing system, resource allocation apparatus comprising:
- storage means indicating the free and assigned states of a plurality of resources, said storage means including a plurality of portions, each portion indicating the free and assigned states of a particular predetermined plurality of said plurality of resources;
a plurality of individually addressable memories, each memory being addressed by a respective one of said portions and being operative in response thereto for providing a corresponding memory output including free resource identifying signals which identify at least a predetermined plurality of the free resources indicated by the applied portion, the memory outputs from said memories also including a plurality of selection signals; and
a plurality of selection means to which said memory outputs are applied, each selection means receiving particular ones of said free resource identifying signals and said selection signals and being operative in response thereto so that the outputs of said selection means select a particular predetermined plurality of the free resources identified by said free resource identifying signals.
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Abstract
Register selection apparatus which includes a plurality of specially mapped programmable memories each addressed by a respective portion of an updatable allocation register which indicates the free and assigned states of a plurality of registers. The resulting memory words read out from the memories are applied to a plurality of multiplexers for identifying a particular predetermined group of registers as being available for assignment. The memory words also provide signals for use in determining whether a sufficient number of free registers are currently available for assignment.
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Citations
11 Claims
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1. For use in a data processing system, resource allocation apparatus comprising:
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storage means indicating the free and assigned states of a plurality of resources, said storage means including a plurality of portions, each portion indicating the free and assigned states of a particular predetermined plurality of said plurality of resources; a plurality of individually addressable memories, each memory being addressed by a respective one of said portions and being operative in response thereto for providing a corresponding memory output including free resource identifying signals which identify at least a predetermined plurality of the free resources indicated by the applied portion, the memory outputs from said memories also including a plurality of selection signals; and a plurality of selection means to which said memory outputs are applied, each selection means receiving particular ones of said free resource identifying signals and said selection signals and being operative in response thereto so that the outputs of said selection means select a particular predetermined plurality of the free resources identified by said free resource identifying signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification