Semiconductor integrated circuit

• US 4,380,021 A
• Filed: 03/21/1980
• Issued: 04/12/1983
• Est. Priority Date: 03/22/1979
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsuyama, Mitsuo, Kitano, Junjiro, Ohhinata, Ichiro
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US06/131,931
• Time in Patent Office: 1,117 Days
• Field of Search: 357/15, 357/52, 357/53, 357/41, 357/35, 357/38
• US Class Current: 257/162
• CPC Class Codes: H01L 27/0722 in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/075 Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
• CPC Class Codes: H01L 27/0766 with Schottky diodes only

Abstract

A semiconductor integrated circuit with a short turn-off time in which a high breakdown voltage semiconductor element and a Schottky barrier diode are fabricated into a semiconductor substrate, is disclosed. In the integrated circuit, within a semiconductor substrate of a first conductivity type, a diffusion layer with a low impurity concentration disposed deeply which is used as one layer of a high breakdown voltage semiconductor element formed by a high breakdown voltage process and a diffusion layer with a high impurity concentration disposed more shallowly than the diffusion layer with a low impurity concentration, are formed so as to partially couple with each other. The diffusion layer with the high impurity concentration is used for both the ohmic contact for the electrode of the diffusion layer with the low impurity concentration and for a guard ring for a Schottky barrier diode. With such a construction, a Schottky barrier diode may be assembled into a high breakdown voltage semiconductor element with a minimum increase of area. Accordingly, the semiconductor integrated circuit obtained has a high degree of integration and a short turn-off time.

Claims

1. A semiconductor integrated circuit comprising:

a semiconductor substrate of a first conductivity type;

at least one first diffusion layer with a low impurity concentration of a second conductivity type opposite to the first conductivity type formed within said substrate;

a second diffusion layer with a high impurity concentration of the first conductivity type formed within said first diffusion layer;

a third diffusion layer with a high impurity concentration of the first conductivity type formed within said substrate;

wiring layers formed on the surfaces of said second and third diffusion layers;

a metal layer directly contacting with said substrate; and

a fourth diffusion layer of the second conductivity type shaped within said substrate like a frame under the peripheral portion of said metal layer and formed more shallowly than said first and said second diffusion layer, in which

a portion of said second diffusion layer overlaps a portion of said first diffusion layer;

said metal layer serves as an external contact wiring layer for said first diffusion layer;

said substrate, said first diffusion layer and said second diffusion layer are used as a collector region, a base region and an emitter region, respectively, thereby to form an NPN transistor;

said third diffusion region is used as an ohmic contact for said collector region; and

said substrate, said metal layer and said fourth diffusion layer are used as a cathode region, an anode region and a guard ring, respectively, thereby to form a Schottky barrier diode.

2. A semiconductor integrated circuit comprising:

a semiconductor substrate of a first conductivity type;

first and second diffusion layers with a low impurity concentration of a second conductivity type opposite to the first conductivity type, which are formed within said substrate;

a third diffusion layer with a high impurity concentration of the second conductivity type formed within said first diffusion layer;

a fourth diffusion layer with a high impurity concentration of the first conductivity type formed within said substrate;

wiring layers formed on said third and fourth diffusion layers;

a metal layer directly contacting with said substrate;

a fifth diffusion layer with a high impurity concentration of the second conductivity type shaped within said substrate like a frame under the peripheral portion of said metal layer and formed more shallowly than said first and second diffusion layers, in which

a portion of said fifth diffusion layer overlaps a portion of said second diffusion layer;

said metal layer is used as an external connection wiring layer for said second diffusion layer;

said substrate, said first diffusion layer and said second diffusion layer are used as a base region, an emitter region and a collector region, respectively, thereby to form a PNP transistor;

said fourth diffusion layer is used as an ohmic contact for said base region; and

said substrate, said metal layer and said fifth diffusion layer are usd as a cathode region, an anode region and a guard ring, respectively, thereby to form a Schottky barrier diode.

3. A semiconductor integrated circuit comprising:

a semiconductor substrate of a first conductivity type;

at least first and second diffusion layers of a second conductivity type opposite to the first conductivity type formed within said substrate;

a third diffusion layer with a high impurity concentration of the second conductivity type formed within said first diffusion layer;

a fourth diffusion layer with a high impurity concentration of the first conductivity type formed within said second diffusion layer;

a fifth diffusion layer with a high impurity concentration of the first conductivity type formed within said substrate;

wiring layers formed on the surfaces of said third, fourth and fifth diffusion layers;

a metal layer directly contacting with said substrate; and

a sixth diffusion layer with a high impurity concentration of the second conductivity type which is shaped within said substrate like a frame and disposed under the peripheral portion of said metal layer and formed more shallowly than said first and second diffusion layers, in which

a portion of said sixth diffusion layer overlaps a portion of said second diffusion layer;

said metal layer is used as an external connection wiring layer for said second diffusion layer;

said first diffusion layer, said substrate, said second diffusion layer and said fourth diffusion layer respectively are used as an anode region, an anode gate region, a cathode gate region and a cathode region, respectively, thereby to form a PNPN switch; and

said substrate, said metal layer, and said sixth diffusion layer are used as a cathode region, an anode region and a guard ring, respectively, thereby to form a Schottky barrier diode.