Massively parallel processor computer

• US 4,380,046 A
• Filed: 05/21/1979
• Issued: 04/12/1983
• Est. Priority Date: 05/21/1979
• Status: Expired due to Term

• Current Assignee: Frosch Robert A Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, Lai-Wo Fung
• Original Assignee: Frosch Robert A Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, Lai-Wo Fung
• Inventors: Frosch, Robert A. Administrator of the National Aeronautics and Space Administration, with respect to an invention of, Fung, Lai-Wo
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US06/041,143
• Time in Patent Office: 1,422 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 235/92 SH
• US Class Current: 712/22
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array, comprises a large number (e.g. 16,384 in a 128×128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered, parallel data, including spatial translation by shifting or "sliding" of bits vertically or horizontally to neighboring processing elements.

Claims

1. An apparatus for processing multidimensional, digital serial-by-bit data characterized by an ordered array of parallel data streams, comprising an ordered array of interconnected parallel processing elements corresponding to all or part of the data streams, and a control unit connected to said processing elements for causing said processing elements to process the data streams in response to a single set of instructions, each of said processing elements comprising a subunit A including means for arithmetic, shifting and memory operations, a subunit B including means for storing data, performing logical operations and sliding the stored data to a similar subunit in a neighboring processing element, a subunit C including means for storing, inputting and outputting data, a subunit D including additional memory means, and a bidirectional bus, all of said subunits being connected to said bidirectional bus for providing communication between said subunits.

2. The apparatus of claim 1, wherein subunit A includes a counter/shift register.

3. The apparatus of claim 2, wherein said counter/shift register includes means for storing bits, means responsive to a first command signal from said control unit for shifting said stored bits, and means responsive to a second command signal from said control unit for digitally adding said stored bits to an incoming bit.

4. The apparatus of claim 2, wherein said counter/shift register comprises a plurality of registers arranged in a closed ring configuration, pointer means for supplying a pointer signal to said register ring for defining the lowest register in said ring, and counter means for successively indexing said pointer means, the lowest register, defined by said pointer means, outputting its content to said common bus.

5. The apparatus of claim 1, wherein subunit D includes a random access memory.

6. The apparatus of claim 1, wherein each of said processing elements further includes a subunit E including means for selectively inhibiting the operability of subunits A and B, said subunit E also being connected to said bus.

7. An apparatus for processing multidimensional, digital serial-by-bit data in the form of an N×

M array of parallel data streams, comprising a first N×

M array of subunits A each including means for arithmetic, shifting and memory operations, a corresponding, second N×

M array of subunits B including means for storing data, performing logical operations and sliding stored data to similar subunits in said array, a corresponding, third N×

M array of subunits C including means for storing, inputting and outputting data, and a corresponding, fourth N×

M array of bidirectional buses, said arrays being interconnected in an ordered fashion, means for transferring data among said subunits and said arrays including said bidirectional buses, and a control unit connected to said arrays for controlling processing of all of said data streams in said first, second and third arrays in accordance with a single set of instructions.

8. An apparatus for processing multidimensional, digital serial-by-bit data in the form of an N×

M array of parallel data streams, comprising an N×

M array of interconnected parallel processing elements corresponding in position, respectively, to the parallel data streams, and a control unit connected to said processing elements responsive to a single set of instructions for causing said array of processing elements to perform identical and simultaneous operations on single bit slices of the parallel data streams, each of said processing elements comprising a subunit A including means for arithmetic, shifting and memory operations, a single bit subunit B for storing a bit and including means for performing logical and sliding operations, a subunit D having additional memory means, and a bidirectional bus, each of said subunits being connected to said bidirectional bus for providing communication between said subunits.

9. The apparatus of claim 8, wherein the memory of subunit D provides for random access.

10. The apparatus of claim 8, wherein said control unit provides means for sliding the data content of a subunit B to another subunit B of a neighboring processing element.

11. The apparatus of claim 8, wherein each processing element further includes a subunit E for inhibiting the operations of said subunits A and B in response to a mask mode command generated by said control unit.

12. The apparatus of claim 8, wherein said subunit A includes a counter/shift-register including means for storing bits, means responsive to a first command signal from a control unit for shifting said stored bits, and means responsive to a second command signal from said control unit for digitally adding said stored bits to an incoming bit.

13. The apparatus of claim 8, wherein said counter/shift-register comprises a plurality of registers arranged in a closed ring configuration, pointer means for supplying a pointer signal to said register ring for defining the lowest register in said ring, and counter means for successively indexing said pointer means, the lowest register, defined by said pointer means, outputting its content to said bidirectional bus.

14. An apparatus for processing multidimensional, digital serial-by-bit data characterized by an ordered array of parallel data streams, comprising an ordered array of interconnected parallel processing elements corresponding to all, or part, of the data streams and a control unit connected to said processing elements for causing said processing elements to process the data streams in response to a single set of instructions, each of said processing elements, in turn, comprising a subunit including a binary counter/shift register, a subunit including logic for sliding data to one of a plurality of adjacent processing elements, a masking subunit for optionally inhibiting a given processing element from responding to a signal from said control unit, a subunit including storage and means for inputting or outputting data from a given processing element, a subunit including additional memory over that provided by the subunit including the binary counter shift register, and a bidirectional bus, all of said subunits being directly connected to said directional bus, said interconnection allowing for communication between said subunits.