Refresh and error detection and correction technique for a data processing system

• US 4,380,812 A
• Filed: 04/25/1980
• Issued: 04/19/1983
• Est. Priority Date: 04/25/1980
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Druke, Michael B., Baxter, Ward II, Van Roekel, John R., Ziegler, Michael L. II
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/143,675
• Time in Patent Office: 1,089 Days
• Field of Search: 371/38, 371/39, 371/37, 371/40, 371/13
• US Class Current: 714/754
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing

Abstract

A data processing system in which the bits of each stored word in a memory thereof are refreshed periodically. At substantially the same time the refresh operation with respect to each word occurs, an error detection operation also occurs and, if an error is detected in a word that is being refreshed, the error is then corrected and the corrected word is written back into the memory. Thus, errors are continuously being checked with no more use of machine time then is required for the refresh operation. Error correction, when necessary, then takes place at a fixed frequency, a limit thereby being placed on the error correction process. If errors in a work are detected when the word is requested for access by a requestor, the error is corrected before the word is supplied to the requestor but the corrected word is not written back into memory at that time, the word in memory being again detected and corrected at its next refresh operation.

Claims

1. In a data processing system having a memory in which binary words, each comprising a plurality of bits, are stored:

refresh means connected to said memory for periodically refreshing the bits of one or more stored words at a selected refresh time interval;

error detection means connected to said memory for detecting an error which may exist in at least one binary bit of one of said one or more stored words the detection thereof being performed at substantially the same time as the refreshing of said one or more stored words;

a single error correcting means connected to said error detection means and responsive to the detection of an error in said one of said one or more stored words for correcting said error when said error has been detected during said refresh operation; and

means connected to said error correcting means and to said memory for writing said corrected word back into said memory.

2. In a data processing system in accordance with claim 1 and further including:

means responsive to a request from a requestor for accessing a stored word in said memory;

said error detecting means is responsive to said accessing means and is further capable of detecting an error in at least one binary bit of said requested stored word at substantially the same time said stored word is requested for access by said requestor;

said single error correcting means is further capable of correcting an error in said stored word which has been so requested for access; and

means responsive to said corrected word from said error correcting means for supplying said corrected word to said requestor, the uncorrected word remaining in said memory until corrected at a subsequent refresh operation.

3. In a data processing system in accordance with claims 1 or 2 wherein said memory comprises a plurality of memory modules in which said words are stored, the binary bits thereof being located at selectable rows and columns in each said memory module;

and further wherein said refresh means includes;

module select means for providing during a refresh operation a module select signal for selecting a specified memory module in which a word is to be refreshed;

row select means for providing during a refresh operation a row select signal to all of said memory modules identifying a specified row in each of said modules; and

column select means for providing during a refresh operation a column address select signal only to said specified module selected for said refresh operation identifying a specified column in said selected module.

4. In a data processing system in accordance with claim 3 wherein:

said column select means provides said column address select signal only to the module specified by said module select signal when a requestor requests that a word be read out from or written into said memory; and

said row select means provides said row address select signal only to the module specified by said module select signal when a requestor requests that a word be read out from or written into said memory.

5. In a data processing system in accordance with claim 4 further including:

means for providing a write enable signal only to the module specified by said module select signal when a corrected word is written back into said memory during a refresh operation or when a requestor requests that a word be written into said memory.

6. In a data processing system in accordance with claim 5 wherein each said memory module includes means for supplying a busy signal when a refresh operation is occurring with respect to the words stored in said module to prevent a requestor from accessing said module during said refresh operation.