Analog to digital converter

• US 4,381,496 A
• Filed: 11/03/1980
• Issued: 04/26/1983
• Est. Priority Date: 11/03/1980
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Carter, Ernest A.
• Primary Examiner(s): Miller, C. D.
• Application Number:
  US06/202,953
• Time in Patent Office: 904 Days
• Field of Search: 340/347 AD, 340/347 DA, 340/347 CC, 324/99 D
• US Class Current: 341/156
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14

Abstract

A successive-approximation charge-redistribution analog-to-digital converter includes a binary weighted capacitive ladder for converting the least significant bits of the binary output representation and a resistive ladder for converting the higher order bits of the output representation. To achieve a half least significant bit shift, the capacitor of lowest capacitance in the ladder having a capacitance C is replaced by first and second capacitors each having a capacitance C/2. Each of these capacitors has a first terminal connected to the input of a comparator. Another input of the first capacitor is coupled to the low reference voltage. The second input of the second capacitor is coupled to one-eighth the high reference voltage during the sample phase and to the low reference voltage when the sample phase is completed. The resulting redistribution of charge which occurs at the input to the comparator is equivalent to minus one-half times the charge corresponding to one least significant bit. Thus, the stored sample to be converted is reduced in voltage by one-half least significant bit.

Claims

1. A successive-approximation analog-to-digital converter comprising:

comparator means for producing an output in response to an input thereto exceeding a predetermined threshold voltage;

a plurality of binary weighted capacitors, including first and second one-half unit capacitors comprising a unit capacitance, each of the capacitors having a first terminal coupled in common to the input of the comparator means, and a second terminal;

voltage reference means for producing at least first and second predetermined reference voltages, and an offset voltage having a predetermined value between the first and second reference voltages;

sample means, operative during a sample phase, for storing a sample of an unknown analog input voltage on the largest of the capacitors while shorting the comparator means, and for simultaneously coupling the second terminals of each of the other capacitors except the first one-half unit capacitor to the first reference voltage while coupling the second terminal of the first one-half unit capacitor to the offset voltage; and

successive-approximation means, operative during a conversion phase following said sample phase, for converting said sample to a binary representation thereof by successively coupling the second terminals of the capacitors, from the largest to the smallest, to the second reference voltage, and, in response to each such coupling which produces the output from the comparator means, recoupling such second terminal to the first reference voltage.

2. An analog-to-digital converter according to claim 1 wherein the successive-approximation means are further characterized as successively coupling the second terminals of each of the capacitors except the second one-half unit capacitor, from the largest to the smallest, to the second reference voltage, and, in response to each such coupling which produces the output from the comparator means, recoupling such second terminal to the first reference voltage.